Abstract: This patent document describes, among other things, techniques, and apparatuses for providing paging carrier selection based on a coverage enhancement level (CEL) and associated carrier specific configuration. In one aspect, a method of wireless communication is disclosed. The method includes receiving, by a wireless device, from a first network node, a paging radio resource specific paging configuration, selecting, by the wireless device, a paging radio resource based on a paging radio resource specific paging configuration, wherein the selecting further uses a wireless device specific paging configuration in case that the wireless device is configured with the wireless device specific paging configuration, and performing a further communication operation based on the paging radio resource that is selected by the wireless device.

Abstract: Presented are systems and methods for enhancing wireless communication device measurements. A wireless communication device may receive a configuration of time information from the wireless communication node. The configuration may comprise a configuration of time information for measurements to be performed by the wireless communication device. The wireless communication device may perform at least one of the measurements according to the configuration.

Abstract: The present disclosure provides methods and devices for intelligent information collection, having the functions of information detection, information collection, information identification, information storage, and information transmission. During the information collection, the device may automatically identify and select target information and store it, and selectively transmit the target information to a specific information receiving terminal in a specific transmission mode.

Abstract: In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

Abstract: This disclosure describes tools capable of generating messages for use in deblocking filtering a video stream, the messages based on prediction parameters extracted from the video stream.

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract: Devices, systems, methods, and other embodiments associated with decoding image data are described. In one embodiment, an apparatus decoding a bitstream includes a parser that parses a command that includes instructions for decoding a syntax element bitstream from the bitstream. The parser functions to identify a number times to repeat the command and to identify a table associated with the syntax element bitstream based, at least in part, on a table identification (ID) in the command. A decoder decodes the syntax element bitstream as specified by the command based, at least in part, on retrieving a value in a table associated with the table ID to generate a syntax element.

Abstract: A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.

Abstract: Embodiments of the present invention include systems and methods for processing and coding image data. In one embodiment, image data is coded using a first image coding process. If a bit rate constraint is satisfied, the image data is output. If the bit rate constraint is not satisfied, the image data is coded using a second different coding process. In one embodiment, the second coding process is a layered coding process. In another embodiment, if the constraint is satisfied, quantization data may be included in the output, and may be coded using layered coding. Variable length coding processes and hardware implementations are further disclosed for efficient image processing.

Abstract: Embodiments of the present invention provide methods and associated architecture of accuracy adaptive and scalable vector graphics rendering including rendering a graphic comprising a plurality of line segments by processing each of the plurality of line segments in a first pass, and processing each of a plurality of pixels through which the plurality of line segments pass in a second pass, automatically detecting one or more rendering errors of the graphic, and correcting the one or more rendering errors. Other embodiments may be described and/or claimed.

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract: This disclosure describes tools capable of generating messages for use in deblocking filtering a video stream, the messages based on prediction parameters extracted from the video stream.

Abstract: Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

Abstract: Embodiments of the present invention include systems and methods for processing and coding image data. In one embodiment, image data is coded using a first image coding process. If a bit rate constraint is satisfied, the image data is output. If the bit rate constraint is not satisfied, the image data is coded using a second different coding process. In one embodiment, the second coding process is a layered coding process. In another embodiment, if the constraint is satisfied, quantization data may be included in the output, and may be coded using layered coding. Variable length coding processes and hardware implementations are further disclosed for efficient image processing.

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.