Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.

Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

Abstract: A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a variable number gradient demosiac process. The process uses a 5×5 neighborhood of sensor pixel data centered at the pixel under consideration. The process calculates a set of gradients corresponding to different directions within the neighborhood of the sensor pixel data. A threshold value is determined and a subset of gradients is selected from the set of gradients that fall below the threshold value. The system calculates estimation values for the missing color value and the actual measured center pixel color value obtained from the sensor data on directions that are within the subset of gradients below the threshold.

Abstract: A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a variable number gradient demosiac process. The process uses a 5×5 neighborhood of sensor pixel data centered at the pixel under consideration. The process calculates a set of gradients corresponding to different directions within the neighborhood of the sensor pixel data. A threshold value is determined and a subset of gradients is selected from the set of gradients that fall below the threshold value. The system calculates estimation values for the missing color value and the actual measured center pixel color value obtained from the sensor data on directions that are within the subset of gradients below the threshold.

Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

Abstract: This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined and performed simultaneously where possible to speed manipulation of the video data. Efficient design of the system allows memory buffers and logic gates to be shared or eliminated to reduce the size, cost and power requirements of the hardware implementation.

Abstract: A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to the devices to cause activation of the events on intended devices.

Abstract: An organic electroluminescent device comprises a lower electrode provided on the surface of a color filter, wherein the lower electrode is directly provided on the surface of an overcoat layer. An isolation layer is further provided between the lower electrode and the overcoat layer, such that the connection between the lower electrode and the color filter can be proceeded beneficially. Besides, the situation of barrier layer broken will be not happened. Thus, the structure completeness of the organic electroluminescent device can be held, and the production yield of that can be improved.

Abstract: A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The video input processor further enables multi-functions such as video image scaling, video image filtering before the video data are output for further video compression.

Abstract: A video compression scheme enables the user to select one of many video compression formats, including the widely-used standard video formats such as MPEG-1, MPEG-2, MPEG-4 and H.263. In one embodiment, the scheme is implemented as a hardware-software combination, with the hardware portion, preferably implemented as an ASIC chip, performing the core compression and the software portion dealing with the detailed formatting. In another embodiment, a 32-bit aligned transitional data format is used.

Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A novel architecture for implementing video processing features a data bus and a control bus. In an embodiment, data transfers between processing modules can take place over the data bus as mediated by a programmable memory copy controller, or through local connections, freeing up the control bus for instructions provided by a processor. A video decoder may be implemented in a system on chip with instructions provided by an off-chip processor. A semaphore or semaphore array mechanism may be used to mediate traffic between the various modules.

Abstract: A video processing system configured with DMA latency compensation is disclosed. This compensation helps minimize or otherwise mitigate shortages of data to the display, thereby improving the quality of displayed video. A relatively small line buffer is used to stage data for video processing. Should an underflow of data occur (where the buffer reading process is ahead of the buffer writing process), data is read from the previous line buffer. This not only prevents shortages of data to the display, but also provides data that is more likely to be relevant to the actual scene being displayed (as compared to random data).

Abstract: A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.

Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a matchblock from the current picture and by determining a spatial offset in a corresponding reference picture which signifies a good prediction of where the current macroblock can be found. Multi-level motion estimation is performed in three stages to refine the resolution of the motion vector with reduced computational bandwidth. First, a matchblock from a reference frame is decomposed equally into several sub-matchblocks, each of which is searched in parallel over a search area decomposed into sub-blocks by a similar factor so as to determine a preliminary motion vector in the reference picture.

Abstract: This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined and performed simultaneously where possible to speed manipulation of the video data. Efficient design of the system allows memory buffers and logic gates to be shared or eliminated to reduce the size, cost and power requirements of the hardware implementation.

Abstract: Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.