Abstract: A label assembly and method of using the same to label articles durably, yet removably. In one embodiment, the label assembly is used to label fabric articles, such as clothing, and comprises (a) an image forming laminate for forming an image on the fabric article, the image forming laminate comprising an ink layer, the ink layer being bondable to the fabric article; and (b) an image removing laminate for removing the image from the fabric article, the image removing laminate comprising a remover layer, the remover layer, upon being activated by heat and/or light, being bondable to the ink layer of the image forming laminate; (c) whereby, upon bonding of the image removing laminate to the ink layer, the bonding between the image removing laminate and the ink layer is stronger than the bonding between the ink layer and the fabric article.

Abstract: A phase-change memory cell structure includes a bottom diode on a substrate; a heating stem on the bottom diode; a first dielectric layer surrounding the heating stem, wherein the first dielectric layer forms a recess around the heating stem; a phase-change storage cap capping the heating stem and the first dielectric layer; and a second dielectric layer covering the first dielectric layer and the phase-change storage cap wherein the second dielectric layer defines an air gap in the recess.

Abstract: A label assembly and method of using the same to label articles durably, yet removably. In one embodiment, the label assembly is used to label fabric articles, such as clothing, and comprises (a) an image forming laminate for forming an image on the fabric article, the image forming laminate comprising an ink layer, the ink layer being bondable to the fabric article; and (b) an image removing laminate for removing the image from the fabric article, the image removing laminate comprising a remover layer, the remover layer, upon being activated by heat and/or light, being bondable to the ink layer of the image forming laminate; (c) whereby, upon bonding of the image removing laminate to the ink layer, the bonding between the image removing laminate and the ink layer is stronger than the bonding between the ink layer and the fabric article.

Abstract: A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer.

Abstract: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

Abstract: An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode.

Abstract: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.

Abstract: In one embodiment, the disclosure relates to a method for forming a semiconductor power device by depositing a first layer of TiW on a gate region and a source region, depositing a second layer of refractory metal over the first layer of TiW at the gate region, depositing a dielectric stack over the second layer of refractory metal and a portion of the first layer of TiW, depositing an etch stop layer over a portion of the dielectric stack, depositing an interconnect layer over the etch stop layer and the dielectric stack and depositing an etch mask over the interconnect layer.

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor.

Abstract: A method for labeling fabrics, such as fabric garments, and a heat-transfer label well-suited for use in said method. In one embodiment, the heat-transfer label comprises (i) a support portion, the support portion comprising a carrier and a release layer; (ii) a wax layer, the wax layer overcoating the release layer; and (iii) a transfer portion, the transfer portion comprising an adhesive layer printed onto the wax layer and an ink design layer printed onto the adhesive layer. Preferably, at least a portion of the ink design layer is printed using a variable printing technique, such as thermal transfer printing.

Abstract: An apparatus for transmitting a file with enhanced transmission security through a network includes a file-splitting processor that splits the file into a plurality of message segments and addresses the plurality of message segments to a plurality of addresses assigned to a receiving host. The apparatus includes a message segment transmitter for transmitting the plurality of message segments to the receiving host.

Abstract: A method for labeling fabrics, such as fabric garments, and a heat-transfer label (311) well-suited for use in said method. In one embodiment, the heat-transfer label (311) comprises (i) a support portion (313), the support portion (313) comprising a carrier (315) and a release layer (317); (ii) a wax layer (319), the wax layer overcoating the release layer (317); and (iii) a transfer portion (321), the transfer portion (321) comprising an adhesive layer (323) printed directly onto the wax layer (319) and an ink design layer (325) printed directly onto the adhesive layer (323). Each of the adhesive layer (323) and the ink design layer includes a non-cross-linked PVC resin. The ink design layer may be screen printed onto the adhesive layer (323) or may be printed onto the adhesive layer (323) using thermal transfer printing, ink jet printing or laser printing.

Abstract: An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.

Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.