Patents by Inventor Li-Ting Wang

Li-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283359
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Patent number: 10276562
    Abstract: According to an exemplary embodiment, a chip is provided. The chip includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Hui-Cheng Chang
  • Publication number: 20190124721
    Abstract: An apparatus, a system and a method are disclosed. An exemplary method includes providing a wafer process chamber and a plurality of radiant heat elements under the wafer process chamber, receiving a wafer holder configured to be used in the wafer process chamber, and processing a wafer located on the wafer holder in the wafer process chamber. The wafer holder includes: a wafer contact portion including an upper surface and a lower surface, an exterior portion including an upper surface and a lower surface, and a tapered region formed in the wafer contact portion.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Patent number: 10157995
    Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Hong-Mao Lee, Huicheng Chang
  • Patent number: 10159112
    Abstract: An apparatus, a system and a method are disclosed. An exemplary method includes providing a wafer process chamber and a plurality of radiant heat elements under the wafer process chamber, receiving a wafer holder configured to be used in the wafer process chamber, and processing a wafer located on the wafer holder in the wafer process chamber. The wafer holder includes: a wafer contact portion including an upper surface and a lower surface, an exterior portion including an upper surface and a lower surface, and a tapered region formed in the wafer contact portion.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Publication number: 20180350655
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Patent number: 10072039
    Abstract: The present invention provides improved processes of preparing Fondaparinux sodium comprising converting a compound of formula ABCDE4 to Fondaparinux sodium at a reaction pH of no more than about 9.0. In some embodiments, the intermediates for the synthesis of Fondaparinux sodium, are also provided.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 11, 2018
    Assignee: ScinoPharm Taiwan, Ltd.
    Inventors: Lung-Huang Kuo, Shang-Hong Chen, Li-Ting Wang, Wen-Li Shih, Yuan-Xiu Liao
  • Publication number: 20180240882
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang PENG, Tai-Chun HUANG, Teng-Chun TSAI, Cheng-Tung LIN, De-Fang CHEN, Li-Ting WANG, Chien-Hsun WANG, Huan-Just LIN, Yung-Cheng LU, Tze-Liang LEE
  • Patent number: 10026658
    Abstract: Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, De-Fang Chen, Huan-Just Lin
  • Patent number: 10006094
    Abstract: Degenerate primers for amplifying fragments of the nucleotide sequences of mutL and dnaJ genes of a lactic acid bacterium of Lactobacillus casei group are provided. Methods and kits for discriminating interspecies and intraspecies of a lactic acid bacteria of Lb. casei group are also provided.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 26, 2018
    Assignee: Food Industry Research And Development Institute
    Inventors: Chien-Hsun Huang, Li-Na Huang, Li-Ting Wang
  • Publication number: 20180151701
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.
    Type: Application
    Filed: March 29, 2017
    Publication date: May 31, 2018
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
  • Patent number: 9966448
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
  • Patent number: 9954069
    Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 9941394
    Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, De-Fang Chen, Hung-Ta Lin, Chien-Hsun Wang
  • Patent number: 9853102
    Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, Cheng-Tung Lin, De-Fang Chen, Chih-Tang Peng, Chien-Hsun Wang, Hung-Ta Lin
  • Publication number: 20170345765
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 9805968
    Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
  • Patent number: 9768044
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9735107
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 9735261
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin