Patents by Inventor Li-Ting Wang

Li-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978344
    Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
  • Publication number: 20210100226
    Abstract: A liver lesion-mouse model which is a liver-specific ISX gene expression and p53 gene knockout transgenic mouse, wherein liver lesion develops after the mouse is fed with a high calorie diet.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 8, 2021
    Applicant: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Shih-Hsien Hsu, Li-Ting Wang, Shen-Nien Wang, Kwei-Yan Liu
  • Publication number: 20210057276
    Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
  • Patent number: 10930783
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
  • Publication number: 20210050430
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
  • Publication number: 20210043684
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Publication number: 20210014702
    Abstract: A data communication system able to provide a speedy response to a user equipment transmitting data includes a base station and a data center. The base station is disposed adjacent to the data center, the base station is coupled between the data center and the user equipment, and the base station transmits data provided by the user equipment to the data center. The data center processes first data from the user equipment, and transmits a second data to the user equipment through the base station. Therefore, the data transmission time between the data center and the user equipment is shortened, and the data can be quickly fed back to the user equipment.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: YAO-TING CHANG, CHAO-KE WEI, TZE-CHERN MAO, LI-WEN CHANG, HUI-HSUAN WANG
  • Publication number: 20210013402
    Abstract: Disclosures of the present invention describe a halide semiconductor memristor that is suitable for being as an artificial synapse. The halide semiconductor memristor comprises a first electrode layer, an active layer and a second electrode layer, wherein the active layer comprises a first oxide semiconductor film formed on the first electrode layer, a halide semiconductor film formed on the first oxide semiconductor film, and a second oxide semiconductor film formed on the halide semiconductor film Moreover, a variety of experimental data have proved that, this halide semiconductor memristor is indeed suitable for being adopted as a plurality of artificial synapses that are used in manufacture of a neuromorphic device, and exhibits many advantages, including: capable of being driven by a low operation voltage, having a multi-stage adjustable resistance state, and a wide dynamic range of the switching resistance states.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 14, 2021
    Inventors: HAO-WU LIN, CHIEN-YU CHEN, TSE-WEI CHEN, LI-WEI CHEN, WEI-CHUN WANG, CHIH-TING HSU
  • Publication number: 20210013104
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Kai JEN, Li-Ting WANG, Yi-Hao CHIEN
  • Patent number: 10854681
    Abstract: A display device includes a pixel circuit substrate, a plurality of light emitting devices, a driver circuit substrate, a plurality of connection terminals, and an electrically conductive adhesion layer. The light emitting devices are electrically connected to the pixel circuit substrate. The driver circuit substrate is disposed on a back side of the pixel circuit substrate. The connection terminals electrically connect the driver circuit substrate to the pixel circuit substrate. The electrically conductive adhesion layer is disposed between the pixel circuit substrate and the driver circuit substrate.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 1, 2020
    Assignee: Au Optronics Corporation
    Inventors: Yung-Chih Chen, Chun-Hsin Liu, Li-Chih Hsu, Tsung-Ying Ke, Wan-Tsang Wang, Keh-Long Hwu, Ya-Ting Hsu
  • Patent number: 10854676
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 10854728
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 10825383
    Abstract: A display device including a first substrate, pixel structures, a second substrate, first signal lines, and second signal lines is provided. The pixel structures are disposed on a first surface of the first substrate. Each of the pixel structures includes a switch element and a pixel electrode. The switch element has a first terminal, a second terminal, and a control terminal. The pixel electrode is electrically connected to the second terminal of the switch element. The second substrate is disposed under a second surface of the first substrate. The first signal lines and the second signal lines are disposed on the second substrate. The first terminals and the control terminals of the switch elements of the pixel structures are respectively electrically connected to the first signal lines and the second signal lines, wherein the first signal lines are substantially parallel to the second signal lines.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 3, 2020
    Assignee: Au Optronics Corporation
    Inventors: Li-Chih Hsu, Yung-Chih Chen, Chun-Hsin Liu, Ya-Ting Hsu, Wan-Lin Chen, Wan-Tsang Wang, Tsung-Ying Ke, Keh-Long Hwu
  • Publication number: 20200335388
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Teng-Chun TSAI, Bing-Hung CHEN, Chien-Hsun WANG, Cheng-Tung LIN, Chih-Tang PENG, De-Fang CHEN, Huan-Just LIN, Li-Ting WANG, Yung-Cheng LU
  • Publication number: 20200279944
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 10763260
    Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
  • Patent number: 10707114
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Publication number: 20200193900
    Abstract: The disclosure provides a display panel including first pixel structures, second pixel structures, first signal lines, second signal lines, a first driving circuit, and a second driving circuit. The first signal lines and the first pixel structures are disposed in a first display area and electrically connected. The second signal lines and the second pixel structures are disposed in a second display area and electrically connected. The first display area and the second display area are arranged in a first direction. The first signal lines and the second signal lines are arranged in a second direction. The first direction and the second direction are perpendicular. The first signal lines and the second signal lines are structurally separated. The first drive circuit is electrically connected to the first signal lines. The second driving circuit is electrically independent from the first driving circuit and electrically connected to the second signal lines.
    Type: Application
    Filed: May 23, 2019
    Publication date: June 18, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yung-Chih Chen, Wan-Lin Chen, Tsung-Ying Ke, Li-Chih Hsu, Ya-Ting Hsu, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu, Chih-Ling Hsueh
  • Patent number: 10670958
    Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n?1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Yu-Cheng Tung, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen