Patents by Inventor Li-Ting Wang
Li-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11594636Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 17, 2022Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20230017768Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20230008413Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.Type: ApplicationFiled: February 16, 2022Publication date: January 12, 2023Inventors: Po-Kang Ho, Kuo-Ju Chen, Wei-Ting Chang, Wei-Fu Wang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo, Yi-Chao Wang, Tsai-Yu Huang
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Patent number: 11532516Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.Type: GrantFiled: April 12, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
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Publication number: 20220384436Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20220328631Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.Type: ApplicationFiled: June 10, 2021Publication date: October 13, 2022Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
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Patent number: 11444028Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.Type: GrantFiled: December 16, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
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Publication number: 20220278097Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11395373Abstract: An apparatus, a system and a method are disclosed. An exemplary method includes providing a wafer process chamber and a plurality of radiant heat elements under the wafer process chamber, receiving a wafer holder configured to be used in the wafer process chamber, and processing a wafer located on the wafer holder in the wafer process chamber. The wafer holder includes: a wafer contact portion including an upper surface and a lower surface, an exterior portion including an upper surface and a lower surface, and a tapered region formed in the wafer contact portion.Type: GrantFiled: December 17, 2018Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
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Patent number: 11384054Abstract: In certain aspects, the invention provides crystalline forms of ivacaftor N-(2,4-di-tert-butyl-phenyl-5-hydroxy-phenyl)-1,4-dihydro-4-oxoquinoline-3-carboxamide. In related aspects, the invention provides a process for preparing any one of crystalline forms S2, S3, S4 and S5 of ivacaftor. The process includes: forming a solution including crude ivacaftor and a solvent; adding an anti-solvent to the solution to form slurry including a precipitate; isolating the precipitate; and drying the precipitate to provide crystalline form S2, S3, S4, or S5 of ivacaftor.Type: GrantFiled: March 12, 2021Date of Patent: July 12, 2022Assignee: ScinoPharm Taiwan, Ltd.Inventors: Kuan-Hsun Huang, Li-Ting Wang, Inze Lin, Tsung-Cheng Hu
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Publication number: 20220173239Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: ApplicationFiled: February 17, 2022Publication date: June 2, 2022Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20220140079Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: January 17, 2022Publication date: May 5, 2022Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20220127234Abstract: In certain aspects, the invention provides crystalline forms of ivacaftor N-(2,4-di-tert-butyl-phenyl-5-hydroxy-phenyl)-1,4-dihydro-4-oxoquinoline-3-carboxamide. In related aspects, the invention provides a process for preparing any one of crystalline forms S2, S3, S4 and S5 of ivacaftor. The process includes: forming a solution including crude ivacaftor and a solvent; adding an anti-solvent to the solution to form slurry including a precipitate; isolating the precipitate; and drying the precipitate to provide crystalline form S2, S3, S4, or S5 of ivacaftor.Type: ApplicationFiled: March 12, 2021Publication date: April 28, 2022Inventors: Kuan-Hsun HUANG, Li-Ting WANG, Inze LIN, Tsung-Cheng HU
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Patent number: 11257952Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: May 18, 2020Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Patent number: 11227788Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.Type: GrantFiled: July 6, 2020Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
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Patent number: 11227918Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: GrantFiled: May 24, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20210327749Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.Type: ApplicationFiled: July 27, 2020Publication date: October 21, 2021Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11101179Abstract: A semiconductor structure includes a semiconductor substrate, a gate stack disposed over the semiconductor substrate, a first oxide spacer disposed along a sidewall of the gate stack, a protection portion disposed over the first oxide spacer, and an interlayer dielectric layer disposed over the semiconductor substrate. The first oxide spacer and the protection portion are disposed between the gate stack and the interlayer dielectric layer.Type: GrantFiled: July 11, 2019Date of Patent: August 24, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Kai Jen, Li-Ting Wang, Yi-Hao Chien
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Publication number: 20210257255Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Inventors: Su-Hao Liu, Wen-Yen Chen, Tz-Shian Chen, Cheng-Jung Sung, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang
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Patent number: 11087808Abstract: Provided is a word-line structure including a substrate, a word line, and an epitaxial pattern. The word line is embedded in the substrate. The word line includes a conductive layer, a barrier layer, an insulating layer, and a gate dielectric layer. The barrier wraps a lower portion of the conductive layer. The insulating layer wraps an upper portion of the conductive layer. The gate dielectric layer surrounds the insulating layer and the barrier layer to electrically isolate the barrier layer from the substrate. The epitaxial pattern is disposed between the insulating layer and the substrate and in contact with the substrate. A memory device including the word-line structure and a method of manufacturing the same are also provided.Type: GrantFiled: July 14, 2020Date of Patent: August 10, 2021Assignee: Winbond Electronics Corp.Inventors: Li-Ting Wang, Ming-Chung Chiang