Abstract: A method includes: The receive end receives 2N channels of signals through N first antennas, where the 2N channels of signals are respectively from N second antennas of the transmit end. When transmission performance of any one of the 2N channels of signals is less than a first threshold, the receive end respectively receives, from two second antennas, two channels of signals whose polarization directions are orthogonal. When transmission performance of the two channels of signals is both greater than a second threshold, the receive end receives the 2N channels of signals through the N first antennas.

Abstract: The present invention is directed to a peptide, multimer, conjugate, analog, derivative or mimetic thereof that inhibits the activity of VISTA. The invention further contemplates therapeutic use of the VISTA antagonist peptide, multimer, conjugate, derivative or mimetic thereof, including treating or preventing cancer, bacterial infections, viral infections, parasitic infections and fungal infections, as well as research uses of the antagonist.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.

Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.

Abstract: A rotary digging drill includes three disk drills arranged in ascending order of diameter, each with a cavity therein. The disk drill includes two circular ring seats arranged side by side, multiple toothed digging buckets disposed at peripheries of the two circular ring seats, and ring gear racks respectively disposed on inner sides of the two circular ring seats. Adjacent ones of the disk drills have the toothed digging buckets facing opposite directions, and the disk drills all rotate in a direction facing a large opening, enabling adjacent two of the three disk drills to rotate in opposite directions. The rotary digging drill further includes three disk drill supports that match the three disk drills in quantity and are configured to support and drive the three disk drills.

Abstract: This disclosure discloses a information display method and apparatus, an electronic device and a storage medium, the information display method includes: acquiring a popularity parameter of an object to be displayed, wherein the object to be displayed is an object not explained currently corresponding to a display page; generating prompt information corresponding to the object to be displayed in response to the popularity parameter of the object to be displayed meeting a prompt condition, wherein the prompt information is configured to reflect popularity of the object to be displayed; and displaying the prompt information on the display page.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate, and first and second epitaxial layers wrapping around the first and second semiconductor fins, respectively. The semiconductor device further includes a contact plug over the first epitaxial layer and the second epitaxial layer. The contact plug includes a first interfacial layer over the first epitaxial layer and a second interfacial layer over the second epitaxial layer. The first and second interfacial layers include a noble metal element and a Group IV element.

Abstract: An electronic device having a central area and a peripheral area surrounding the central area is provided. The electronic device includes a substrate, a through hole, a buffer layer, a first circuit structure, an electronic component and a first pad. The substrate has a first surface and a second surface opposite to the first surface. The through hole penetrates through the substrate and has a first through hole and a second through hole. The buffer layer covers the first surface, the second surface, an inner wall of the first through hole and an inner wall of the second through hole. The first circuit structure is disposed on the first surface. The first through hole corresponds to the central area, the second through hole corresponds to the peripheral area, and a width of the second through hole is greater than a width of the first through hole.

Abstract: Disclosed is an image segmentation method, including: obtaining an original image set; performing feature extraction on the original image set by using a backbone network to obtain a feature map set; performing channel extraction fusion processing on the feature map set by using a channel extraction fusion model to obtain an enhanced feature map set; and segmenting the enhanced feature map set by using a preset convolutional neural network to obtain an image segmentation result. In addition, the present application also provides an image segmentation system and device, and a readable storage medium, which have the beneficial effects above.

Abstract: The present application discloses a person re-identification method, system and device, and a computer-readable storage medium. The method includes: obtaining a first type of person image without a label; making label information for the first type of person image; training a target person re-identification network on the basis of the first type of person image and the label information to obtain a first trained target person re-identification network; extracting a region of interest in the first type of person image; and training, on the basis of the first type of person image and the region of interest, the first trained target person re-identification network to obtain a second trained target person re-identification network, and performing person re-identification on the basis of the target person re-identification network.

Abstract: Disclosed in the present disclosure is a method for smelting a high-temperature alloy with an ultrahigh N content in a VIM furnace, and a high-temperature alloy with an ultrahigh N content. The VIM-furnace smelting method comprises a smelting step performed in a VIM furnace, and a casting step, wherein at a later stage of smelting, a nitrogen-containing substance is added to the VIM furnace to adjust the content of N. In the present disclosure, by comprehensively improving the raw materials, the smelting process, etc., the yield of N during a VIM-furnace smelting process is increased and accurate control over the content of N in the high-temperature alloy is achieved, such that a target content of nitrogen can be guaranteed, and an ideal product can thus be obtained.

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: Methods and systems are provided for characterizing connate water salinity and resistivity of a subsurface formation. Well log data including resistivity and spontaneous potential (SP) log data are measured by at least one downhole tool disposed within a borehole. The resistivity and SP log data are inverted to determine a resistivity model and an SP model, which are used to determine connate water resistivity. The connate water resistivity is used to determine connate water salinity. The connate water salinity derived from the inversion of resistivity log data and SP log data (or derived from a trained ML system supplied with such log data) can be used as a baseline measure of connate water salinity, and this baseline measure can be evaluated together with the connate water salinity estimates derived from pulsed neutron tool measurements over time-lapsed periods of production to monitor variation in connate water salinity due to production.

Abstract: Embodiments of the present disclosure provide an encoding and decoding method, apparatus and device.

Abstract: An organic light emitting diode display substrate, comprises: a base substrate, and a first data line, a driving thin film transistor and an energy storage capacitor, wherein the energy storage capacitor comprises a first capacitor plate and a second capacitor plate disposed opposite to each other, and the second capacitor plate is electrically connected to a gate of the driving thin film transistor, in a direction away from the base substrate, the first capacitor plate is disposed between the first data line and the second capacitor plate. The display substrate further comprises a shielding portion. The shielding portion is between the second capacitor plate and the first data line in a direction perpendicular to the base substrate, and the organic light emitting diode display substrate further comprises a first thin film transistor and a second thin film transistor.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.

Abstract: Provided in the present application are a disk processing method and system, and an electronic device. The method comprises: when disk alarm information is detected, marking a corresponding alarm disk as a faulty disk; detecting the state of a disk group corresponding to the faulty disk; if the state of the disk group is degraded, marking the faulty disk as an isolation disk, and generating alarm information; if the state of the disk group is healthy, determining whether there is a redundant disk group; if there is no redundant disk group, operating the faulty disk according to a first preset rule, and generating alarm information; and if there is a redundant disk group, detecting the state of the redundant disk group, if the state of the redundant disk group is healthy, marking the faulty disk as the isolation disk, and generating alarm information, otherwise, operating the faulty disk according to a second preset rule, and generating alarm information.

Abstract: A display panel and a display device are provided. The display panel includes a base substrate and a pixel driving circuit provided on a side of the base substrate, and the pixel driving circuit includes a driving transistor, ninth transistor, eighth transistor, first transistor and second transistor. A first electrode of the ninth transistor is connected to a third initial signal line and a second electrode of the ninth transistor is connected to a first electrode of the driving transistor. A first electrode of the eighth transistor is connected to a gate electrode of the driving transistor. A first electrode of the first transistor is connected to a first initial signal line and a second electrode of the first transistor is connected to a second electrode of the eighth transistor. A first electrode of the second transistor is connected to the second electrode of the eighth transistor and a second electrode of the second transistor is connected to a second electrode of the driving transistor.