Abstract: An active noise control system and associated auto-selection method for modeling a secondary path for the active noise control system are provided. The method includes the steps of: receiving a reference signal; filtering the reference signal with a secondary-path estimation filter to obtain a filtered reference signal, wherein the secondary path estimation filter is determined from a plurality of candidate secondary-path estimation filters; filtering the reference signal with an adaptive filter to provide a compensation signal; sensing a residual noise signal at a listening position of the active noise control system; and adapting filter coefficients of the adaptive filter according to the residual noise signal and the filtered reference signal.

Abstract: An active noise control system and associated auto-selection method for modeling a secondary path for the active noise control system are provided. The method includes the steps of: receiving a reference signal; filtering the reference signal with a secondary-path estimation filter to obtain a filtered reference signal, wherein the secondary path estimation filter is determined from a plurality of candidate secondary-path estimation filters; filtering the reference signal with an adaptive filter to provide a compensation signal; sensing a residual noise signal at a listening position of the active noise control system; and adapting filter coefficients of the adaptive filter according to the residual noise signal and the filtered reference signal.

Abstract: A photographic apparatus with supplemental light adjusting function and the supplemental light adjusting method used in the same are provided. The photographic apparatus comprises a light source and a photographic element. The method comprises steps of: photographing by the photographic element; illuminating by the light source once the operating condition of a default photographing mode is conformed, and reaching a first supplemental light intensity by the light source within a first length of time; completing photographing by the photographic element once the light source reaches a second supplemental light intensity which is greater than the first supplemental light intensity.

Abstract: A photographic apparatus with supplemental light adjusting function and the supplemental light adjusting method used in the same are provided. The photographic apparatus comprises a light source and a photographic element. The method comprises steps of: photographing by the photographic element; illuminating by the light source once the operating condition of a default photographing mode is conformed, and reaching a first supplemental light intensity by the light source within a first length of time; completing photographing by the photographic element once the light source reaches a second supplemental light intensity which is greater than the first supplemental light intensity.

Abstract: A handheld electronic device includes a main body, an antenna, a gravity sensor and a control circuit. The main body has an operation surface. The operation surface has a first side and a second side opposite to each other. The antenna is disposed in the main body and located near the first side. The gravity sensor is disposed in the main body and capable of sensing a tilted state of the main body relative to a gravity direction. The control circuit is electrically connected to the antenna and the gravity sensor. When a position of the first side is higher than a position of the second side and an included angle between the operation surface and the gravity direction is between 0 degree and a predetermined value, the control circuit increases power of the antenna.

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract: A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.

Abstract: Voice processing methods and systems are provided. An utterance is received. The utterance is compared with teaching materials according to at least one matching algorithm to obtain a plurality of matching values corresponding to a plurality of voice units of the utterance. Respective voice units are scored in at least one first scoring item according to the matching values and a personified voice scoring algorithm. The personified voice scoring algorithm is generated according to training utterances corresponding to at least one training sentence in a phonetic-balanced sentence set of a plurality of learners and at least one real teacher, and scores corresponding to the respective voice units of the training utterances of the learners in the first scoring item provided by the real teacher.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: An optical film assembly includes a first prism film and a first diffusing film. The first diffusing film is disposed on the first prism film. The first prism film has a plurality of prism structures arranged in parallel with each other and arranged in an orientation direction. The first diffusing film has a tensile direction. An angle included between the tensile direction of the first diffusing film and the orientation direction of the prism structures of the first prism film is between 50 degrees and 130 degrees.

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract: The invention discloses a porous composite biomaterial comprising of poly(?-glutamic acid)-g-chondroitin sulfate (?-PGA-g-CS) copolymer and poly(?-caprolactone). The composite biomaterial provides a three-dimensional microenviroment for using as a scaffold for tissue engineering and for supporting the attachment and proliferation of cells. The invention also discloses a method of producing a porous composite biomaterial.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate.

Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.

Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.

Abstract: An electronic device is provided. The electronic device includes a housing, a rotating mechanism and a first rotating member. The rotating mechanism, rotatably disposed in the housing, rotatable along a first direction and a second direction different from the first direction. The first rotating member, disposed on the housing, rotatable between a first position and a second position. When the first rotating member is in the first position, the first rotating member engages with the rotating mechanism. When the rotating mechanism rotates along the first direction, the rotating mechanism is separated from the first rotating member, whereinafter, the first rotating member is able to rotate from the first position to the second position.

Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.