Patents by Inventor Liang-An Lin

Liang-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705440
    Abstract: A micro LED display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. Each of the pixel regions includes a plurality of sub-pixel regions. The micro LEDs are located on the driving substrate. At least one of the sub-pixel regions is provided with two micro LEDs of the micro LEDs electrically connected in series, and a dominant wavelength of the two micro LEDs is within a wavelength range of a specific color light. In a repaired sub-pixel region of the sub-pixel regions, only one of the two micro LEDs emits light. In a normal sub-pixel region of the sub-pixel regions, both of the two micro LEDs emit light.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: July 18, 2023
    Assignee: PlayNitride Inc.
    Inventors: Kuan-Yung Liao, Ching-Liang Lin, Yun-Li Li, Yu-Chu Li
  • Publication number: 20230217551
    Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent impedance. The detection unit detects the resonant tank current and the resonant tank voltage to acquire associated parameters. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates an impedance value of the resonant tank equivalent impedance according to the inductance of the resonant tank equivalent inductor, a time difference, the resonant period, a reference current value, a negative peak current value and a second expression.
    Type: Application
    Filed: March 8, 2022
    Publication date: July 6, 2023
    Inventors: Ming-Shi Huang, Zheng-Feng Li, Jhih-Cheng Hu, Yi-Liang Lin, Yu-Min Meng, Chun-Wei Lin, Chun Chang, Thiam Wee Tan
  • Publication number: 20230213591
    Abstract: A power detection circuit is provided for detecting current total input power of a resonant circuit. The power detection circuit includes a detection circuit and an estimation circuit. The detection circuit receives a current signal and obtains resonant-slot baseband power according to the current signal to generate the baseband power value. The current signal represents a resonant-slot current generated by the resonant circuit. The estimation circuit receives the baseband power value and estimates the current total input power according to the baseband power value to generate an estimated power value.
    Type: Application
    Filed: April 25, 2022
    Publication date: July 6, 2023
    Inventors: Ming-Shi HUANG, Zheng-Feng LI, Jhih-Cheng HU, Yi-Liang LIN, Yu-Min MENG, Chun-Wei LIN, Chun CHANG, Thiam-Wee TAN
  • Publication number: 20230213159
    Abstract: A light-emitting assembly, a method for adjusting the light-emitting assembly, and a vehicle. The light-emitting assembly is used for a vehicle and includes a seat and a support, a light-emitting module being held on the support. A first adjustment mechanism is provided for performing a first adjustment on the light-emitting module, and a second adjustment mechanism is provided for performing a second adjustment on the light-emitting module. The support and the seat are pivotally connected together, so that the support can pivot around a horizontal axis under the action of the first adjustment mechanism.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 6, 2023
    Applicant: VALEO VISION
    Inventors: Xin ZHANG, Liang LIN, Zhao FANG, Lihua ZENG, Jianmin YUAN
  • Publication number: 20230215792
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang
  • Publication number: 20230208132
    Abstract: A voltage stabilizer is provided for stabilizing a gate-source voltage of a switching element, wherein a source of the switching element receives a first driving voltage. The voltage stabilizer includes a bipolar junction transistor, a first resistor and a second resistor. A base of the bipolar junction transistor receives a second driving voltage, a collector of the bipolar junction transistor is electrically connected to a gate of the switching element, a first terminal of the first resistor is electrically connected to the collector and the gate, a second terminal of the first resistor is electrically connected to the source of the switching element and receives the first driving voltage, a first terminal of the second resistor is electrically connected to an emitter of the bipolar junction transistor, and a second terminal of the second resistor receives a third driving voltage The bipolar junction transistor is operated in an active region.
    Type: Application
    Filed: April 21, 2022
    Publication date: June 29, 2023
    Inventors: Kuan-Ting Lee, Chen-Chieh Kao, Yu-Liang Lin, Cheng-Chia Hsiao
  • Publication number: 20230207313
    Abstract: A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.
    Type: Application
    Filed: May 24, 2022
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
  • Publication number: 20230198466
    Abstract: An oscillation circuit including an amplifier, a feedback resistor and a first switch circuit is provided. The amplifier inverts and amplifies an oscillation signal received from an input terminal thereof to provide an output oscillation signal at an output terminal thereof. The feedback resistor is coupled between the input terminal and the output terminal, and coupled with the first switch circuit in parallel. The first switch circuit conducts the input terminal to the output terminal in one of the following situations: (1) an input voltage of the oscillation signal is higher than an output voltage of the output oscillation signal by at least a first threshold value; and (2) the output voltage is higher than the input voltage by at least a second threshold value. The first switch circuit has a first on-state resistance smaller than a resistance of the feedback resistor.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Ping-Yuan DENG, Chia-Liang LIN, Ka-Un CHAN
  • Patent number: 11682599
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11682655
    Abstract: A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20230170218
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11664457
    Abstract: The invention provides a display device and a method of manufacturing a thin film transistor. The method of manufacturing a thin film transistor comprises: (A) providing a substrate; (B) forming a light shielding layer on the substrate, and patterning the light shielding layer to form a patterned light shielding layer; (C) forming a buffer layer on the substrate; (D) forming a semiconductor layer on the substrate, and patterning the semiconductor layer to form a patterned semiconductor layer; (E) forming an insulating layer on the substrate; and (F) forming a conductive layer on the substrate, and patterning the conductive layer to form a patterned conductive layer; wherein the same mask is used for patterning the light shielding layer and the semiconductor layer. Photoelectric effect of the thin film transistor outside the display region can be effectively avoided, while reducing the number of masks in the production process.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 30, 2023
    Assignees: AU OPTRONICS (KUSHAN) CO., LTD., AU OPTRONICS CORPORATION
    Inventors: Chin-Chuan Liu, Fu-Liang Lin
  • Patent number: 11663690
    Abstract: A video processing method includes: decoding apart of a bitstream to generate a decoded frame, where the decoded frame is a projection-based frame that includes projection faces in a projection layout; and remapping sample locations of the projection-based frame to locations on the sphere, where a sample location within the projection-based frame is converted into a local sample location within a projection face packed in the projection-based frame; in response to adjustment criteria being met, an adjusted local sample location within the projection face is generated by applying adjustment to at least one coordinate value of the local sample location within the projection face, and the adjusted local sample location within the projection face is remapped to a location on the sphere; and in response to the adjustment criteria not being met, the local sample location within the projection face is remapped to a location on the sphere.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 30, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ya-Hsuan Lee, Jian-Liang Lin
  • Patent number: 11664325
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Patent number: 11654203
    Abstract: Disclosed herein are a dual-targeted carbonic anhydrase IX complex, a contrast agent comprising the same, and a synthesizing method thereof. The dual-targeted carbonic anhydrase IX complex includes a carbonic anhydrase IX (CA9) binding peptide, a sulfonamide derivative, and a metal chelating agent. The dual-targeted carbonic anhydrase IX complex has potential for use as a molecular nuclear drug.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 23, 2023
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Siao-Syun Guan, Tsai-Yueh Luo, Tse-Zung Liao, Cheng-Liang Peng, Kun-Liang Lin
  • Patent number: 11659206
    Abstract: A video decoding method includes: decoding a part of a bitstream to generate a decoded frame, and parsing at least one syntax element from the bitstream. The decoded frame is a projection-based frame that includes projection faces packed in a cube-based projection layout. At least a portion of a 360-degree content of a sphere is mapped to the projection faces via cube-based projection. The at least one syntax element is indicative of a guard band configuration of the projection-based frame.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 23, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ya-Hsuan Lee, Jian-Liang Lin
  • Patent number: 11651972
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Patent number: 11645693
    Abstract: An example method of complementary consumer item selection includes: receiving, by a computer system, an image representing a first consumer item of a reference set of consumer items; identifying a target category of a complementary consumer item to be associated with the reference set of consumer items; generating, by a neural network processing the set of images, a feature embeddings representing the first consumer item in relation to the target category; selecting, using the feature embedding, from a set of available consumer items, a plurality of candidate consumer items associated with the target category; and selecting, among the plurality of candidate consumer items, the complementary consumer item to be associated with the reference set of consumer items.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 9, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Yen-Liang Lin, Son Tran, Larry Davis
  • Publication number: 20230134560
    Abstract: The present disclosure relates an integrated chip structure. The integrated chip structure includes a bottom electrode disposed within a dielectric structure over a substrate. A top electrode is disposed within the dielectric structure over the bottom electrode. A switching layer and an ion source layer are between the bottom electrode and the top electrode. A barrier structure is between the bottom electrode and the top electrode. The barrier structure includes a metal nitride configured to mitigate a thermal diffusion of metal during a high temperature fabrication process.
    Type: Application
    Filed: March 14, 2022
    Publication date: May 4, 2023
    Inventors: Chia-Wen Zhong, Yen-Liang Lin, Yao-Wen Chang
  • Publication number: 20230136060
    Abstract: The method is capable of effectively labeling the nanodiamonds with radioactive gallium and can be operated at room temperature, and therefore is convenient to operate and does not require further purification to obtain the nanodiamonds labelled with radioactive gallium with a purity of at least 99%
    Type: Application
    Filed: October 10, 2022
    Publication date: May 4, 2023
    Inventors: MEI-HUI WANG, KUN-LIANG LIN, CHUAN-YI CHIEN, HUNG-MAN YU