Patents by Inventor Liang-An Lin

Liang-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854955
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11855118
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11848208
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
  • Publication number: 20230402403
    Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Kuan Liang Liu, Shin-Puu Jeng
  • Publication number: 20230403828
    Abstract: A water cooling assembly is configured to be mounted at an electrical connector of a circuit board. The water cooling assembly includes a mounting plate and a water cooling radiator. The mounting plate includes a mounting portion and a plugging portion. The plugging portion is connected to a side of the mounting portion, and the plugging portion is configured to be inserted into the electrical connector of the circuit board. The water cooling radiator is fastened to the mounting portion of the mounting plate.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Applicant: COOLER MASTER CO., LTD.
    Inventors: Chien-Liang LIN, Shui-Fa TSAI
  • Patent number: 11840774
    Abstract: The present disclosure discloses a one-step chitosan fiber spinning device, including a stand; a stock solution tank, a coagulating bath, a plasticizing stretch bath, a water washing basin, a drying mechanism and a winding mechanism; a front end of a water conveying pipe is fixed on an inner wall of a front end of the water washing basin; a bearing at a front end of a mounting sleeve is mounted on the inner wall of the front end of the water washing basin; activity slots are formed in outer ends of mounting plates; a control head is fixed at an outer end of a control head seat; one end of a two-shaft motor is connected with a gear; a water tank is mounted at a top of a rear end of the water conveying pipe.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 12, 2023
    Assignee: WENZHOU JIAYUAN BIOTECHNOLOGY CO. LTD
    Inventors: Liang Lin, Xinxu Yan, Rui Han, Peng Guo
  • Patent number: 11843007
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20230395521
    Abstract: An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20230395581
    Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20230392294
    Abstract: The present disclosure discloses a method for preparing a pure chitosan fiber, and relates to the technical field of preparation of chitosan. The method includes the following steps: S1, preparing an acetic acid solution; S2, preparing a chitosan stock solution; S3, treating a chitosan spinning solution; and S4, preparing a chitosan fiber. In step S3, a pretreatment machine includes a body; an driving mechanism is arranged in the body; a stirring mechanism is arranged in the driving mechanism; a scraping mechanism is arranged below the driving mechanism; a preliminary treatment mechanism is arranged at an inner upper side of the body; the driving mechanism penetrates through the preliminary treatment mechanism and is arranged in the body; a separation mechanism is arranged on a bottom of the body.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Liang Lin, Rui Han, Peng Guo, Xinxu Yan
  • Patent number: 11836214
    Abstract: A matrix calculation device including a storing unit, a multiply accumulate (MAC) circuit, a pre-fetch circuit, and a control circuit, and an operation method thereof are provided. The storing unit stores a first and second matrixes. The MAC circuit is configured to execute MAC calculation. The pre-fetch circuit pre-fetches at least one column of the first matrix from the storing unit to act as pre-fetch data, pre-fetches at least one row of the second matrix from the storing unit to act as the pre-fetch data, or pre-fetches at least one column of the first matrix and at least one row of the second matrix from the storing unit to act as the pre-fetch data. The control circuit decides whether to perform the MAC calculation on a current column of the first matrix and a current row of the second matrix through the MAC circuit according to the pre-fetch data.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 5, 2023
    Assignee: NEUCHIPS CORPORATION
    Inventors: Chiung-Liang Lin, Chao-Yang Kao
  • Publication number: 20230386984
    Abstract: First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Ying-Ju Chen, Shin-Puu Jeng
  • Publication number: 20230387172
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20230386946
    Abstract: A semiconductor structure includes a packaging substrate containing at least one trench located between a first region and a second region, a first chip module bonded to the first region of the packaging substrate through first solder material portions, and a second chip module bonded to the second region of the packaging substrate through second solder material portions. A first underfill material portion laterally surrounds the first solder material portions and extends into a first portion of the at least one trench. A second underfill material portion laterally surrounds the second solder material portions and extends into a second portion of the at least one trench. The at least one trench is used to absorb stress to the underfill material portions.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20230383442
    Abstract: The present disclosure discloses a one-step chitosan fiber spinning device, including a stand; a stock solution tank, a coagulating bath, a plasticizing stretch bath, a water washing basin, a drying mechanism and a winding mechanism; a front end of a water conveying pipe is fixed on an inner wall of a front end of the water washing basin; a bearing at a front end of a mounting sleeve is mounted on the inner wall of the front end of the water washing basin; activity slots are formed in outer ends of mounting plates; a control head is fixed at an outer end of a control head seat; one end of a two-shaft motor is connected with a gear; a water tank is mounted at a top of a rear end of the water conveying pipe.
    Type: Application
    Filed: June 5, 2023
    Publication date: November 30, 2023
    Inventors: Liang Lin, Xinxu Yan, Rui Han, Peng Guo
  • Publication number: 20230386988
    Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Li-Ling Liao, Ming-Chih Yew, Po-Chen Lai, Chia-Kuei Hsu, Shin-Puu Jeng, Meng-Liang Lin
  • Publication number: 20230387028
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Publication number: 20230386956
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Publication number: 20230378205
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20230378116
    Abstract: Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin