Patents by Inventor Liang-Chen Lin
Liang-Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230290769Abstract: A semiconductor device includes: a core region of core circuitry over a substrate; an input/output (I/O) region of interfacing circuitry over a substrate and coupled to the core region; a sealing ring having first, second and third sides, the sealing ring surrounding, and being isolated from, the core region and the I/O region; an intra-communication (intra-com) stack including intra-com segments in corresponding metallization layers which are stacked, the intra-com segments correspondingly extending between, and thereby coupling, the core region and the I/O region; and a first parapet on the intra-com stack and which extends from the first side to the third side of the sealing ring the first parapet being between, and isolated from each of, the core region and the I/O region.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventor: Liang-Chen LIN
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Patent number: 11742276Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.Type: GrantFiled: April 20, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Huan Chu, Hsu-Hsien Chen, Liang-Chen Lin, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai
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Patent number: 11676958Abstract: A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.Type: GrantFiled: March 26, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Liang-Chen Lin
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Publication number: 20220310585Abstract: A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventor: Liang-Chen LIN
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Publication number: 20220246511Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Huan Chu, Hsu-Hsien Chen, Liang-Chen Lin, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai
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Patent number: 11315860Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.Type: GrantFiled: October 17, 2019Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Huan Chu, Hsu-Hsien Chen, Liang-Chen Lin, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai
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Patent number: 11226363Abstract: A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.Type: GrantFiled: November 22, 2019Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu
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Patent number: 11164825Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.Type: GrantFiled: October 15, 2019Date of Patent: November 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Liang-Chen Lin, Shih-Cheng Chang
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Publication number: 20210118789Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Huan Chu, Hsu-Hsien Chen, Liang-Chen Lin, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong TSAI
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Patent number: 10847492Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.Type: GrantFiled: June 25, 2018Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jyun-Lin Wu, Liang-Chen Lin, Shiang-Ruei Su
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Publication number: 20200135667Abstract: An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.Type: ApplicationFiled: October 15, 2019Publication date: April 30, 2020Inventors: Liang-Chen LIN, Shih-Cheng CHANG
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Publication number: 20200088786Abstract: A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Inventors: Shiang-Ruei SU, Liang-Chen LIN, Chia-Wei TU
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Publication number: 20190393186Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Inventors: Jyun-Lin WU, Liang-Chen LIN, Shiang-Ruei SU
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Patent number: 10495687Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.Type: GrantFiled: November 28, 2016Date of Patent: December 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu
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Patent number: 10014252Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.Type: GrantFiled: July 1, 2016Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
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Patent number: 9711474Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.Type: GrantFiled: September 24, 2014Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Gia-Her Lu, Liang-Chen Lin, Tung-Chin Yeh, Jyun-Lin Wu, Tung-Jiun Wu
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Publication number: 20170074923Abstract: Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventors: Shiang-Ruei SU, Liang-Chen LIN, Chia-Wei TU
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Patent number: 9508617Abstract: A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.Type: GrantFiled: March 2, 2012Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shiang-Ruei Su, Liang-Chen Lin, Chia-Wei Tu
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Publication number: 20160315050Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
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Patent number: 9385079Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.Type: GrantFiled: July 17, 2014Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu