Abstract: A system and method of generating three-dimensional (3D) depth information is disclosed. The vanishing point of a two-dimensional (2D) input image is detected based on vanishing lines. The 2D image is classified and segmented into structures based on detected edges. The classified structures are then respectively assigned depth information.

Abstract: A system and method of generating three-dimensional (3D) depth information is disclosed. A classification and segmentation unit segments a two-dimensional (2D) image into a number of segments, such that pixels having similar characteristics are classified into the same segment. A spatial-domain texel density analysis unit performs texel density analysis on the 2D image to obtain textual density. A depth assignment unit assigns depth information to the 2D image according to the analyzed textual density.

Abstract: The invention presents a system and method for obtaining object depth through digital signal processing. The auto depth-field capturing method for a camera includes the steps of a) taking plural images; b) estimating plural epipolar data of the plural images for obtaining a matrix describing motion and directional vectors; c) estimating a location data in response to the plural epipolar data and the matrix; d) rectifying the plural images corresponding to the plural epipolar data for obtaining plural rectified images; e) calculating the location data for obtaining disparity vectors of the rectified images; f) obtaining a depth map in response to the disparity vectors and the location data; and g) painting a 3D image in correspondence with the depth map. The depth estimation method of the present invention is fully automatic without change of the camera itself.

Abstract: A driving support system with plural dimension processing units (DPUs) for indicating a condition of a surrounding area is disclosed. The driving support system of a vehicle includes plural image capturing devices disposed around the vehicle; at least a dimension processing unit (DPU) connected with the plural image capturing devices for receiving images from the plural image capturing devices and then producing plural related depth maps; a controller connected with the DPU for receiving the plural related depth maps and then producing an indicating data; and a display device connected with the controller for displaying the indicating data around the vehicle in a vertical view.

Abstract: The invention presents a single lens auto focus system of stereo image generation and a method thereof. The stereo three-dimensional (3D) image capturing method of a single lens auto focus camera, includes the steps of a) taking plural multi-focus images; b) estimating the plural multi-focus images to obtain a depth map and an all-in-focus image; c) mixing the depth map with plural background depth maps to obtain a mixed depth map; d) obtaining respectively a left image for left eye of user and a right image for right eye of user by means of depth image based rendering (DIBR); and e) outputting the left image and the right image, thereby displaying a stereo image onto a 3D display.

Abstract: An image rectification method for a video device includes receiving an image that is a facial image of a transmitter from the transmitter, obtaining a first angular deviation with respect to line of sight of the transmitter according to the image, obtaining a second horizontal angular deviation and a second vertical angular deviation with respect to line of sight of a receiver using the video device, and performing an image synthesis procedure on the image according to the first angular deviation, the second horizontal angular deviation and the second vertical angular deviation, for generating an eye-to-eye image sent to the receiver.

Abstract: A method of optimizing a compression of a still image in JPEG 2000 format, which includes the steps of: (a) dividing an image into a predetermined numbers of tiles each having a predetermined numbers of tile pixels; (b) decomposing each of the tiles into a predetermined number of subbands by Discrete Wavelet Transform (DWT); (c) partitioning each of the subbands into a predetermined number of code-blocks which are arranged into a plurality of bit-planes respectively; (d) minimizing a total rate with a given predetermined total distortion of image so as to pre-determine an optimal truncation point for each of the code-blocks; (e) truncating a predetermined part of the DWT coefficients for each of the code-blocks so as to reduce computational resource; and (f) encoding each of the code-blocks by embedded block-coding to form an embedded code-stream having a plurality of code passes.

Abstract: The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720 p resolution pictures at 30 fps in real time.

Abstract: The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720p resolution pictures at 30 fps in real time.

Abstract: The invention presents a single lens auto focus system of stereo image generation and a method thereof. The stereo three-dimensional (3D) image capturing method of a single lens auto focus camera, includes the steps of a) taking plural multi-focus images; b) estimating the plural multi-focus images to obtain a depth map and an all-in-focus image; c) mixing the depth map with plural background depth maps to obtain a mixed depth map; d) obtaining respectively a left image for left eye of user and a right image for right eye of user by means of depth image based rendering (DIBR); and e) outputting the left image and the right image, thereby displaying a stereo image onto a 3D display.

Abstract: The invention provides a video coding method. The method may include: receiving a set of video data for transmission; identifying at least two partitions from the video data, a first partition containing at least a portion of decoding information enabling a decoding of the video data, and a second partition containing at least a portion of information indicative of video content; encoding at least a portion of the first partition at an application layer of a system to generate partition protection information, the partition protection information allowing a recovery of first partition data when an error occurs to the first partition data; and transmitting the first partition, the partition protection information, and the second partition.

Abstract: A data reuse method with level C+ for block matching motion estimation is disclosed. Compared to conventional Level C scheme, this invention can save large external memory bandwidth of motion estimation. The main idea is to reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction. Several vertical successive current macroblocks are stitched, and the searching region of these current macroblocks is loaded, simultaneously. With the small overhead of internal memory, the reduction of external memory bandwidth is large. By case studies of H.264/AVC, the level C+ scheme can provide a good trade-off between the conventional Level C and D scheme.

Abstract: This invention presented a universal de-interlacing method and system by the motion detection, the motion adaptive interpolation, the directional edge interpolation, the 3:2 pull-downed detection and the 3:2 Pull-Downed recovery. Four-field motion detection can detect the motion area and the still area. By cooperating with the motion adaptive interpolation and the directional edge interpolation the picture possesses the very clear quality, high contrast, and high resolution. The 3:2 pull-downed detection and the 3:2 Pull-Downed recovery can detect the 3:2 Pull-Downed movie sequence and recover the interlaced fields into a progressive frames universally without too much overhead of computational power.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.

Abstract: A method of optimizing a compression of a still image in JPEG 2000 format, which includes the steps of: (a) dividing an image into a predetermined numbers of tiles each having a predetermined numbers of tile pixels; (b) decomposing each of the tiles into a predetermined number of subbands by Discrete Wavelet Transform (DWT); (c) partitioning each of the subbands into a predetermined number of code-blocks which are arranged into a plurality of bit-planes respectively; (d) minimizing a total rate with a given predetermined total distortion of image so as to pre-determine an optimal truncation point for each of the code-blocks; (e) truncating a predetermined part of the DWT coefficients for each of the code-blocks so as to reduce computational resource; and (f) encoding each of the code-blocks by embedded block-coding to form an embedded code-stream having a plurality of code passes.

Abstract: The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720p resolution pictures at 30 fps in real time.

Abstract: This invention presented a universal de-interlacing method and system by the motion detection, the motion adaptive interpolation, the directional edge interpolation, the 3:2 pull-downed detection and the 3:2 Pull-Downed recovery. Four-field motion detection can detect the motion area and the still area. By cooperating with the motion adaptive interpolation and the directional edge interpolation the picture possesses the very clear quality, high contrast, and high resolution. The 3:2 pull-downed detection and the 3:2 Pull-Downed recovery can detect the 3:2 Pull-Downed movie sequence and recover the interlaced fields into a progressive frames universally without too much overhead of computational power.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay.

Abstract: A global elimination algorithm for motion estimation and the hardware architecture thereof that can efficiently remove the braches in the data flow, so that the data flow is smoothened and is more adapted for hardware implementation. Because the processing time for each motion vector is fixed, preliminary prediction can be eliminated. The elimination ratio of the search locations will not be varied with time change and thus can be increased. The global elimination algorithm can produce a search result of high accuracy that is identical to that of a full-search block matching algorithm. The peak signal-to-noise ratio of global elimination algorithm is at times better than that of full-search block matching algorithm. Compared with other architectures based on the full-search block matching algorithm, the hardware architecture of the present invention can provide a best computational capability for each logic gate, while the power consumption of logic gates is minimum under the same throughput of motion vector.

Abstract: An architecture for performing the two-dimensional discrete wavelet transform includes a transform module including a first stage and a second stage for decomposing an input image into four bands, and among the four bands, the band having the low frequency in both horizontal and vertical direction serves as the input image for next level decomposition operation; a multiplexer for selecting the band having the low frequency in both horizontal and vertical direction as the input image to feed into the transform module; and an optional memory module for storing the band having the lowest frequency in both horizontal and vertical direction.