Abstract: A Universal Variable Length Code (UVLC) encoder for H.26L is provided. This encoder is simple and efficient due to the change of codeword number and codeword alignment technique. The look-up table could absorb the effect of codeword number's change on the previous stage of H.26L encoding. And there is no side effect on complexity of the whole system. The header information coding and byte alignment function could also be integrated in this architecture.

Abstract: The invention describes a simple and efficient codeword degrouping algorithm which can be applied in an MPEG audio decoder, in which a codeword is degrouped into three samples. According to the proposed algorithm, the division and modulo computations applied in the original degrouping method can be fully substituted into the addition and subtraction computations by using the mode selection and iterative decompositions, and thus largely reduces the overhead and complexity for the decoder. Also, an efficient architecture for the proposed algorithm includes one special adder, two subtractors, and two adders. The architecture generates the quotient and remainder simultaneously with fix-rate throughput.

Abstract: A CMOS active pixel sensor with motion detection includes a photo diode, a reset switch, two sample and hold circuits, and two readout circuits. Each sample and hold circuit includes a MOS switch and a capacitor. The readout circuit includes a source follower and a row select switch. The two sample and hold circuits can store current frame pixel data as well as previous frame pixel data, and these two image data can be read out by the two readout circuits. Therefore, the frame difference can be directly obtained in differential mode. This CMOS active pixel sensor can be used in single chip camera systems with motion detection and video compression functions. Furthermore, because of the low supply voltage consideration in the pixel circuit, this CMOS active pixel sensor is suitable for low power applications.

Abstract: An MPEG-II audio decoder with a synthesis subband filter includes a fast IMDCT (Inverse Modified Discrete Cosine Transform) module and an IPQMF (Inverse Pseudo Quadrature Mirror Filter) module. The fast IMDCT module involves a butterfly stage of input subband samples which requires only about ¼ the amount of multiplier-accumulate computation of the ISO suggested method. The IPQMF module involves an efficient memory configuration which requires only half size of the standard synthesis subband filter bank.

Abstract: A hardware structure for inverse quantization and multichannel processing in MPEG-2 audio decoding is provided, which includes 5 groups of first-in-first-out (abbreviated as FIFO) registers, each group of which has 3 FIFO registers and are connected in series; a multiplier capable for receiving an internal data processing feedback from the last FIFO group of FIFO registers; a single register; a first adder/subtractor capable for receiving a feedback from the first group of FIFO registers and its output being fed to the first group of FIFO registers; a second adder/subtractor capable for receiving a feedback from a second group of FIFO registers. The second group of FIFO registers stores an output from the second adder/subtractor or an output from the first group of FIFO registers; a third group of FIFO registers stores an output from the single register or an output from the second group of FIFO registers; a fourth group of FIFO registers stores an output from the third group of FIFO registers; and so on.

Abstract: A motion estimator, employing a three-step hierarchical search block-matching algorithm for obtaining a motion vector by block-matching between a current block and its corresponding block, is provided. The motion estimator comprises: a memory block, a matching unit and a control unit. The memory block is for storing a candidate block corresponding to the current block. The matching unit matches the size of a current block with aforementioned candidate block and sub-candidate blocks identical to the current block. The control unit supplies candidate blocks in the memory blocks to the matching unit according to a prescribed matching sequence, and writes the candidate block corresponding to the current block to the section no longer used in the memory block simultaneous to the performance of Step 3 of a three-step hierarchical search block-matching algorithm.

Abstract: We discloses an efficient method for compressing a color image, visual block pattern truncation coding (VBPTC), in which the conventional block truncation coding (BTC) serves to encode an original image. This method defines the edge block according to human visual perception. If the difference between the two quantized values of BTC in a block is larger than a threshold which is defined by visual characteristics, the block will be identified as an edge block. In an edge block, the bitmap is adapted to compute block gradient orientation and to match the block pattern.

Abstract: The invention discloses a 9-cell array architecture with data-rings for 3-step hierarchical search (3SHS) block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator tree-like structure can be used to simply internal I/O controller and reduce latency. In addition, we can utilize techniques to reduce external memory accesses and interconnections. The results demonstrate that the array architecture with the data-rings is low in terms of latency, memory bandwidth and costs and a high performance solution for the 3 SHS.

Abstract: The invention of the "high-frequency CMOS dual/multi modulus prescaler" is a new application in this field. Compared to other transistors which have CMOS technology, this invention has a greater potential for high frequency operations. Additionally, it has a low-power consumption property and can be easily integrated with CMOS technology. We propose a general construction of the prescaler which can be applied to dual-modulus prescaler. First, a divide-by-3/4 dual-modulus prescaler and a divide-by-4/5 one are presented. Consequently, a general dual-modulus prescaler is developed based on the same technique. Moreover, a general multi-modulus prescaler will also be achieved. The operating frequency can be up to 1 GHz for the proposed dual/multiple modulus prescalers which are fabricated in a 0.8-.mu.m SPDM CMOS technology.