Abstract: Embodiments of the disclosure provide methods and systems for performing machine learning. The method can include: receiving training data; training a machine learning model based on the training data, wherein the machine learning model includes multiple layers each having one or more nodes having one or more connections with a node from another layer of the machine learning model; evaluating weights associated with the connections of the machine learning model, wherein each connection has a corresponding weight; removing, from the machine learning model, one or more connections having a weight that does not satisfy a threshold condition; and after the connections have been removed, updating the machine learning model.

Abstract: A system configured to detect malware is described. The system configured to detect malware including a data collector configured to detect at least a first hypertext transfer object in a chain of a plurality of hypertext transfer objects. The data collector further configured to analyze at least the first hypertext transfer object for one or more events. And, the data collector configured to generate a list of events based on the analysis of at least the first hypertext transfer object.

Abstract: A new hammering system with electromagnetic power for dynamic pile testing. The basic working principle of the hammering system is as follows: when an internal coil is energized, a magnetic force is generated to attract tightly, via a magnetic conduction panel, an adaptive weight hammer disposed in contact with the surface of the panel; when the internal coil is de-energized, demagnetization occurs, and the weight hammer falls instantaneously to impact the pile top, thereby achieving the effects of a stable weight hammer and quick attraction and falling of the hammer. A clamping scale is arranged inside an adjustment section of a guide frame. A falling height of the weight hammer may be selected arbitrarily.

Abstract: Provided herein are methods, systems, devices, and computer-readable storage media for selecting a detection area for a well (e.g., as part of an assay plate) comprising a plurality of encoded microcarriers. In some aspects, selecting the detection area includes obtaining one or more images of the well; calculating a center of the well according to a two-dimensional coordinate system; assigning a position, according to the two-dimensional coordinate system, of a first encoded microcarrier from the plurality; determining whether a distance between the position of the first encoded microcarrier and the center of the well according to the two-dimensional coordinate system exceeds a threshold distance; and including in the detection area one or more microcarriers whose distance from the center of the well does not exceed the threshold distance, while excluding those whose distance from the center of the well exceeds the threshold.

Abstract: An electronic device may include an antenna having a resonating element, an antenna ground, and a feed. First and second tunable components may be coupled to the resonating element. Adjustable matching circuitry may be coupled to the feed. Control circuitry may use the first tunable component to tune a midband antenna resonance when sensor circuitry identifies that the device is being held in a right hand and may use the second tunable component to tune the midband resonance when the sensor circuitry identifies that the device is being held in a left hand. For tuning a low band resonance, the control circuitry may place the antenna in different tuning states by sequentially adjusting a selected one of the matching circuitry and the tunable components, potentially reverting to a previous tuning state at each step in the sequence. This may ensure that antenna efficiency is satisfactory regardless of antenna loading conditions.

Abstract: A system configured to detect malware is described. The system configured to detect malware including a data collector configured to detect at least a first hypertext transfer object in a chain of a plurality of hypertext transfer objects. The data collector further configured to analyze at least the first hypertext transfer object for one or more events. And, the data collector configured to generate a list of events based on the analysis of at least the first hypertext transfer object.

Abstract: A shaft structure includes a rotation shaft, a transmission structure coupled to the rotation shaft, and a moving structure coupled to the transmission structure. The rotation shaft includes a first transmission member fixedly arranged on the rotation shaft. The transmission structure rotates along with the rotation shaft, and includes a second transmission member engaged with the first transmission member. The moving structure moves translationally with respect to the rotation shaft in response to a rotation of the transmission structure.

Abstract: A cross-media search method using a VGG convolutional neural network (VGG net) to extract image features. The 4096-dimensional feature of a seventh fully-connected layer (fc7) in the VGG net, after processing by a ReLU activation function, serves as image features. A Fisher Vector based on Word2vec is utilized to extract text features. Semantic matching is performed on heterogeneous images and the text features by means of logistic regression. A correlation between the two heterogeneous features, which are images and text, is found by means of semantic matching based on logistic regression, and thus cross-media search is achieved. The feature extraction method can effectively indicate deep semantics of image and text, improve cross-media search accuracy, and thus greatly improve the cross-media search effect.

Abstract: The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.

Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.

Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Abstract: The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.

Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.

Abstract: A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

Abstract: An electronic device may be provided with wireless circuitry and control circuitry. The wireless circuitry may include an antenna with an inverted-F antenna resonating element formed from portions of a peripheral conductive electronic device housing structure and may have an antenna ground that is separated from the antenna resonating element by a gap. The antenna may include a first adjustable component coupled between the antenna resonating element arm and the antenna ground on a first side of the antenna feed and a second adjustable component coupled between the antenna resonating element arm and the antenna ground on a second side of the antenna feed. Control circuitry in the electronic device may adjust the first and second adjustable components between a first tuning mode, a second tuning mode, and a third tuning mode.

Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more dual-frequency dual-polarization patch antennas. Each patch antenna may have a patch antenna resonating element that lies in a plane and a ground that lies in a different parallel plane. The patch antenna resonating element may have a first feed located along a first central axis and a second feed located along a second central axis that is perpendicular to the first central axis. The patch antenna resonating element may be rectangular, may be oval, or may have other shapes. A shorting pin may be located at an intersecting point between the first and second axes. The patch antennas may be used in beam steering arrays. The patch antennas may be used for wireless power transfer at microwave frequencies or other frequencies and may be used to support millimeter wave communications.

Abstract: An electronic device may be provided with wireless circuitry and control circuitry. The wireless circuitry may include an antenna with an inverted-F antenna resonating element formed from portions of a peripheral conductive electronic device housing structure and may have an antenna ground that is separated from the antenna resonating element by a gap. The antenna may include a first adjustable component coupled between the antenna resonating element arm and the antenna ground on a first side of the antenna feed and a second adjustable component coupled between the antenna resonating element arm and the antenna ground on a second side of the antenna feed. Control circuitry in the electronic device may adjust the first and second adjustable components between a first tuning mode, a second tuning mode, and a third tuning mode.

Abstract: A flash memory device includes a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, a gap structure between the gate structures, and a second isolation region filling an upper portion of the gap structure and leaving a first air gap in a lower portion of the gap structure.

Abstract: A method for testing a composite service is provided. The method may include installing a first debug probe on a first service. The method may include installing a second debug probe on a second service. The method may include executing the composite service, whereby the composite service comprises the first service and the second service. The method may include receiving a first service interaction log and a second service interaction log, whereby the first interaction log records a first plurality of I/O, and whereby the second interaction log records a second plurality of I/O. The method may include generating a global scheduling script based on the first service interaction log and the second interaction log. The method may include sending the first plurality of I/O to the first debug probe and the second plurality of I/O to the second debug probe based on the global scheduling script.