Abstract: A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Abstract: A rotating shaft configured to connect two screen-brackets includes two axle structures arranged symmetrically. One of the two axle structures includes an axle, a motion conversion structure, a screen bracket connection structure, and a supporting bracket. The axle includes a worm groove at a surface of the axle. The motion conversion structure cooperates with the worm groove to form a worm drive. The screen bracket connection structure is movably connected to the motion conversion structure and includes mounting holes, which are configured to mount the screen-brackets. The supporting bracket is sleeved at the axle, rotates around an axis of the axle, and is movably connected to the motion conversion structure and the screen bracket connection structure. The motion conversion structure is movable along an axis direction of the axle on a first surface relative to the supporting bracket.

Abstract: A two-dimensional (2D) convolutional accelerator generates three-dimensional (3D) results by computing a plurality of running dot product totals for a plurality of shift positions for the frames in a sliding frame group such that each shift position has a running dot product total, and storing the plurality of running dot product totals in the elements of an output array.

Abstract: A new hammering system with electromagnetic power for dynamic pile testing. The basic working principle of the hammering system is as follows: when an internal coil is energized, a magnetic force is generated to attract tightly, via a magnetic conduction panel, an adaptive weight hammer disposed in contact with the surface of the panel; when the internal coil is de-energized, demagnetization occurs, and the weight hammer falls instantaneously to impact the pile top, thereby achieving the effects of a stable weight hammer and quick attraction and falling of the hammer. A clamping scale is arranged inside an adjustment section of a guide frame. A falling height of the weight hammer may be selected arbitrarily.

Abstract: A device may obtain first data relating to a machine learning model. The device may pre-process the first data to alter the first data to generate second data. The device may process the second data to select a set of features from the second data. The device may analyze the set of features to evaluate a plurality of types of machine learning models with respect to the set of features. The device may select a particular type of machine learning model for the set of features based on analyzing the set of features to evaluate the plurality of types of machine learning models. The device may tune a set of parameters of the particular type of machine learning model to train the machine learning model. The device may receive third data for prediction. The device may provide a prediction using the particular type of machine learning model.

Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Abstract: A two-dimensional (2D) convolutional accelerator generates three-dimensional (3D) results by computing a plurality of running dot product totals for a plurality of shift positions for the frames in a sliding frame group such that each shift position has a running dot product total, and storing the plurality of running dot product totals in the elements of an output array.

Abstract: The present invention relates to a fluorescent polymer cast on the surface of wells of a plate and a plate comprising the fluorescent polymer. The plate is used in a method for calibrating read-out values of plate readers. The method for calibrating the plate readers can effectively reduce the deviation of read-out values among different plate readers.

Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.

Abstract: Provided are a service gateway and a method for generating secure name records. The method may commence with receiving a name service request from a host. The name service request may include a name. The method may further include obtaining a service server name record from a name service server. The service server name record may include a plurality of name entries corresponding to the name. The method may then continue with generating a plurality of service gateway name records using the name and the plurality of name entries. The method may further include sending a service gateway name record of the plurality of service gateway name records to the host as a response to the name service request.

Abstract: A method for operating a device for handling a phone call is disclosed. In one aspect the method comprises (a) receiving a phone call from a calling party, (b) determining an action to be performed by the device among a predetermined list of actions related to the handling of a phone call, as a function at least of identity information about the calling party, and (c) performing the determined action for handling the phone call. The device may be programmable and mobile, e.g., a smartphone.

Abstract: A self-driving vehicle system comprising a body having one or more motorized wheels, and a sensor head coupled to the body. The sensor head is movable from a retracted position to an extended position relative to the body. The sensor head comprises one or more proximity sensors and one or more cameras.

Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.

Abstract: An electronic device may include control circuitry, sensors, and wireless circuitry having antennas. The sensors may generate sensor data that is used by the control circuitry to identify an operating environment for the device. The sensor data may include a grip map generated by a touch-sensitive display, infrared facial recognition image signals or other image signals, an angle of arrival of sound received by a set of microphones, impedance data from an impedance sensor, and any other desired sensor data. The control circuitry may use the sensor data, radio-frequency spatial ranging data, information about whether audio is being played over an ear speaker, and/or information about communications protocols in use to identify the operating environment. The control circuitry may adjust antenna settings for the wireless circuitry based on the identified operating environment to ensure that the antennas operate with satisfactory antenna efficiency regardless of operating conditions.

Abstract: A cross-media search method using a VGG convolutional neural network (VGG net) to extract image features. The 4096-dimensional feature of a seventh fully-connected layer (fc7) in the VGG net, after processing by a ReLU activation function, serves as image features. A Fisher Vector based on Word2vec is utilized to extract text features. Semantic matching is performed on heterogeneous images and the text features by means of logistic regression. A correlation between the two heterogeneous features, which are images and text, is found by means of semantic matching based on logistic regression, and thus cross-media search is achieved. The feature extraction method can effectively indicate deep semantics of image and text, improve cross-media search accuracy, and thus greatly improve the cross-media search effect.

Abstract: An electronic device may include control circuitry, sensors, and wireless circuitry having antennas. The sensors may generate sensor data that is used by the control circuitry to identify an operating environment for the device. The sensor data may include a grip map generated by a touch-sensitive display, infrared facial recognition image signals or other image signals, an angle of arrival of sound received by a set of microphones, impedance data from an impedance sensor, and any other desired sensor data. The control circuitry may use the sensor data, radio-frequency spatial ranging data, information about whether audio is being played over an ear speaker, and/or information about communications protocols in use to identify the operating environment. The control circuitry may adjust antenna settings for the wireless circuitry based on the identified operating environment to ensure that the antennas operate with satisfactory antenna efficiency regardless of operating conditions.

Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Abstract: Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.