Patents by Inventor Liang-Kai Han

Liang-Kai Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6369434
    Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kai Chen, Scott W. Crowder, Liang-Kai Han, Michael J. Hargrove, Kam-Leung Lee, Hung Y. Ng
  • Patent number: 6335262
    Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Scott W. Crowder, Anthony Gene Domenicucci, Liang-Kai Han, Michael John Hargrove, Paul Andrew Ronsheim
  • Patent number: 6297127
    Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: October 2, 2001
    Assignee: International Business Machines Corporation
    Inventors: Bomy A. Chen, Liang-Kai Han, Robert Hannon, Jay G. Harrington, Herbert L. Ho, Hsing-Jen Wann
  • Patent number: 6258673
    Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Houlihan, Liang-Kai Han, Dale W. Martin
  • Patent number: 6096580
    Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: August 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: S. Sundar Kumar Iyer, Liang-Kai Han, Robert Hannon, Subramanian S. Iyer, Mukesh V. Khare
  • Patent number: 5578848
    Abstract: High quality, ultra thin SiO.sub.2 /Si.sub.3 N.sub.4 (ON) dielectric layers have been fabricated by in situ multiprocessing and low pressure rapid-thermal N.sub.2 O-reoxidation (LRTNO) of Si.sub.3 N.sub.4 films. Si.sub.3 N.sub.4 film was deposited on the RTN-treated polysilicon by rapid-thermal chemical vapor deposition (RT-CVD) using SiH.sub.4 and NH.sub.3, followed by in situ low pressure rapid-thermal reoxidation in N.sub.2 O (LRTNO) or in O.sub.2 (LRTO) ambient. Results show that ultra thin (T.sub.ox,eq =.about.29 .ANG.) ON stacked film capacitors with LRTNO have excellent electrical properties, and reliability.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: November 26, 1996
    Assignee: Regents of the University of Texas System
    Inventors: Dim-Lee Kwong, Giwan Yoon, Jonghan Kim, Liang-Kai Han, Jiang Yan
  • Patent number: 5478765
    Abstract: High quality, ultra thin (<30 .ANG.) SiO.sub.2 /Si.sub.3 N.sub.4 (ON) dielectric layers have been fabricated by in situ multiprocessing and low pressure rapid-thermal N.sub.2 O-reoxidation (LRTNO) of Si.sub.3 N.sub.4 films. Si.sub.3 N.sub.4 film was deposited on the RTN-treated polysilicon by rapid-thermal chemical vapor deposition (RT-CVD) using SiH.sub.4 and NH.sub.3, followed by in situ low pressure rapid-thermal reoxidation in N.sub.2 O (LRTNO) or in O.sub.2 (LRTO) ambient. Results show that ultra thin (T.sub.ox,eq =.about.29.ANG.) ON stacked film capacitors with LRTNO have excellent electrical properties and reliability.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: December 26, 1995
    Assignee: Regents of the University of Texas System
    Inventors: Dim-Lee Kwong, Giwan Yoon, Jonghan Kim, Liang-Kai Han, Jiang Yan