Abstract: A display device includes a display panel and a switch panel. The switch panel includes a first substrate disposed on the display panel, a shielding pattern layer, a light transmitting layer, pixel electrodes disposed on the light transmitting layer, a second substrate disposed on the pixel electrodes, and the liquid crystal layer disposed between the first substrate and the second substrate. The shielding pattern layer is disposed on the first substrate and includes opening parts and light shielding parts arranged alternately with the opening parts. Each of the light shielding parts has a first thickness. The light transmitting layer is disposed on the shielding pattern layer and includes filling parts filling the opening parts and extending parts arranged alternately with the filling parts. Each of the filling parts has a second thickness greater than the first thickness.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: The present disclosure provides an image sensor and a method of manufacturing the same. The image sensor includes a substrate and a gate electrode. The gate electrode is disposed proximate to a first side of the substrate. The gate electrode includes a first gate portion, a second gate portion, and a third gate portion. The first gate portion is disposed over the first side of the substrate. The second gate portion is disposed within the substrate and connected to the first gate portion. The third gate portion is disposed below and connected to the second gate portion. A first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.

Abstract: The present disclosure relates to a multivalent glyco-complex, an imaging agent and uses thereof. The multivalent glyco-complex includes a plurality of glucose molecules, each of which connects to a central nitrogen atom through a linker, and a chelating group G. The multivalent glyco-complex can be used as an imaging agent to diagnose cancers and to evaluate the therapeutic efficacy of cancers.

Abstract: Disclosed are an output network of a Doherty amplifier, a Doherty amplifier including the output network, and a design method of the Doherty amplifier. The output network includes a combination node, a main output network connected between an output port of the main amplifier and the combination node, an auxiliary output network connected between an output port of the auxiliary amplifier and the combination nod, and a merging matching network connected between the combination node and a radio frequency output port of the Doherty amplifier, where the merging matching network is configured for the node impedance at the combination node being a complex impedance, and the main output network and the auxiliary output network are configured for the node impedance matching with goal load impedances of the main amplifier and the auxiliary amplifier.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: The present disclosure provides for endonuclease enzymes having distinguishing domain features, as well as methods of using such enzymes or variants thereof.

Abstract: A semiconductor package includes a chiplet, a first underfill surrounding the chiplet, and a first encapsulant laterally covering the first underfill. The chiplet includes a semiconductor substrate and die connectors disposed over the semiconductor substrate. The first underfill includes first fillers, and a portion of the first fillers has a substantially planar surface at a first surface of the first underfill. The first encapsulant includes a first surface and a second surface opposite to the first surface, the first surface is substantially leveled with surfaces of the die connectors, and the second surface is substantially leveled with the first surface of the first underfill.

Abstract: A semiconductor package includes an interposer including a first redistribution structure, a first semiconductor die electrically coupled to the first redistribution structure through conductive joints, and a first encapsulant disposed on the first redistribution structure and laterally covering the first semiconductor die. The first semiconductor die includes a semiconductor substrate including a first side facing the first redistribution structure and a second side opposite to the first side, a through substrate via provided within the semiconductor substrate, and a passive device disposed between the second side of the semiconductor substrate and the conductive joints.

Abstract: A semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed over the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, where the first gate extension has a first depth measured from a top surface of the substrate. The semiconductor structure further includes a second gate extension protruding from the gate structure into the second isolation structure, where the second gate extension has a second depth that is different from the first depth.

Abstract: A method is provided. The method includes determining a first hotspot region of a contact structure map. The method includes enlarging, according to a first predefined enlargement profile, the first hotspot region to determine a first enlarged region of the contact structure map. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cropped region, of the contact structure map, that excludes the first portion of the first enlarged region. The method includes updating a first patterned oxide layer map based upon the cropped region to generate an updated patterned oxide layer map.

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes a first region including a gate electrode disposed over a semiconductor fin, a second region, and a border region disposed between the first and second regions. The border region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed over the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. A top surface of the second conductive layer and a top surface of the gate electrode may be substantially co-planar.

Abstract: A light emitting device including an epitaxial structure and a plurality of surface microstructures is provided. The epitaxial structure has a light emitting surface and a surrounding wall surface. The surrounding wall surface surrounds and is connected to the light emitting surface. The plurality of surface microstructures are separately arranged on the light emitting surface along a plurality of directions. The plurality of directions are not perpendicular to the surrounding wall surface. A light emitting device substrate including a plurality of the light emitting device is also provided.

Abstract: A device for decoding encoded video data is configured to determine that a chroma block of the encoded video data is coded in a cross-component prediction (CCP) mode; generate a merge candidate list for the chroma block, wherein the merge candidate list includes at least two prediction candidates generated by different CCP modes and a third prediction candidate, wherein the third prediction candidate comprises a fusion prediction candidate; receive, in the encoded video data, a syntax element set to a value; select a prediction candidate from the merge candidate list based on the value of the syntax element; determine a prediction block for the chroma block based on the selected prediction candidate; determine a decoded block of video data based on the prediction block for the chroma block; and output a decoded picture of video data that includes the decoded block of video data.

Abstract: A video decoder may be configured to receive a first instance of a flag for a first block, with a first value for the flag indicating that a cross-component prediction (CCP) mode is derived without signaling and a second value for the flag indicating that the CCP mode is signaled; in response to determining that the first instance of the flag is set to the first value, derive a first CCP mode for the first block; determine a first predicted chroma block for the first block using the first CCP mode; determine a decoded version of the first block based on the first predicted chroma block; and output a picture of decoded video data that includes the decoded version of the first block.

Abstract: A manufacturing method of a transformer includes: winding a first winding wire around a bobbin, wherein two ends of the first winding wire are connected to a first and a second pin of the bobbin respectively; winding a second winding wire around the bobbin, wherein two ends of the second winding wire are connected to a third and a fourth pin of the bobbin respectively; and winding a third and a fourth winding wire in parallel around the bobbin, wherein two ends of the third winding wire are connected to the second and a fifth pin of the bobbin respectively, and two ends of the fourth winding wire are connected to the fifth and a sixth pin respectively. The first, the third and the fourth winding wires form a primary coil, and the second winding wire is a secondary coil.

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Abstract: A wafer defect detection device adapted for detecting a sample to be tested including two detection features is provided. The wafer defect detection device includes a stage adapted for holding the sample to be tested, a light source module configured to output a detection light to the sample to be tested and reflect a reflected light, and an image sensor disposed on a path of the reflected light and adapted for receiving an image frame. The detection light includes spectra of a first light and a second light, which have two different peak wavelengths. The spectrum of the first light is adapted for detecting one of the detection features. The spectrum of the second light is adapted for detecting other one of the detection features. Luminous intensities of the first light and the second light are independently controlled. The reflected light includes the image frame, which displays the detection features.

Abstract: The invention provides a touch display panel and a manufacturing method therefor. The touch display panel comprises a substrate; a display region disposed on the substrate; an opening region disposed on the substrate and adjacent to the display region; a plurality of touch electrodes disposed in the display region; a plurality of signal lines electrically connected to the touch electrodes; a common voltage loop surrounding the display region and having a first portion and a second portion spaced apart and adjacent to the opening region; a connection structure disposed between the first portion and the second portion; and a plurality of first dummy signal lines electrically connected to the connection structure; wherein the first portion is electrically connected to the second portion through the connection structure.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.