Abstract: The invention provides a touch display panel and a manufacturing method therefor. The touch display panel comprises a substrate; a display region disposed on the substrate; an opening region disposed on the substrate and adjacent to the display region; a plurality of touch electrodes disposed in the display region; a plurality of signal lines electrically connected to the touch electrodes; a common voltage loop surrounding the display region and having a first portion and a second portion spaced apart and adjacent to the opening region; a connection structure disposed between the first portion and the second portion; and a plurality of first dummy signal lines electrically connected to the connection structure; wherein the first portion is electrically connected to the second portion through the connection structure.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: An embodiment is a method including forming a first die, the forming including forming through vias in a first substrate. The method also includes forming a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias. The method also includes forming a first set of die connectors over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate. The method also includes bonding the first die to a second die. The method also includes encapsulating the first die with a first encapsulant. The method also includes forming a second set of die connectors over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors.

Abstract: Disclosed are a power amplifier and a method for controlling a power amplifier. The method includes providing an input signal to the first amplification path and the second amplification path; and supplying a first DC bias voltage and a second DC bias voltage to a control port of the third transistor and a control port of the fourth transistor respectively, where current conduction trenches of the third transistor and the fourth transistor comprise same materials and the first DC bias voltage is higher than the second DC bias voltage.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: The invention provides a display panel, comprising: a substrate having a peripheral area and a display area adjacent to each other, the display area provided with a plurality of pixel units; a gate driving unit provided in the peripheral area; a connection unit provided between the gate driving unit and the display area, and electrically connected to the gate driving unit and the plurality of pixel unit; and a shielding unit provided on the connection unit; wherein a projection area of the connection unit on the substrate corresponds to a projection area of the shielding unit on the substrate, and the shielding unit is electrically connected to a fixed potential.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include an interposer, at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molding portion contacting the second surface of the interposer and laterally surrounding the package substrate. The package substrate may be laterally-confined with respect to the interposer such that at least one horizontal dimension of the package substrate may be less than the corresponding horizontal dimension of the interposer. In various embodiments, reliability of the bonding connections between the interposer and the package substrate may be improved thereby providing increased yields and improved package performance.

Abstract: Systems and methods are described for recommending pairs or sets of clothing items for an individual to wear together, including learning a compatibility metric personalized to each individual. A framework is used to learn compatibility that is personalized to the user based on initial item feedback that may be received from the user via user interfaces that prompt the user to indicate whether the user would wear certain clothing items together and/or individually.

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.

Abstract: A semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.

Abstract: The present disclosure relates to use of 10?(Z), 13?(E), 15?(E)-Heptadecatrienyl hydroquinone compound (hereafter “HQ17(3)”) represented by the following Formula (12), a pharmaceutically acceptable salt, and/or a solvate and/or a hydrate thereof, and a pharmaceutical composition comprising the above compound, in treating coronavirus infection and diseases caused by the infection, especially SARS-COV-2 infection.

Abstract: A system for purifying helium gas, a method, and an application. The system includes a first gas-liquid separation device, a primary helium extraction tower, a second gas-liquid separation device, a secondary helium extraction tower, and a nitrogen removal tower, which are in sequential communication. The first gas-liquid separation device performs first treatment to convert helium-containing natural gas into a first gas and first liquid phases; the primary helium extraction tower performs first distillation on the first gas and first liquid phases to obtain a second gas and second liquid phases; the second gas-liquid separation device performs second treatment to convert the second gas phase to a third gas and third liquid phase; the secondary helium extraction tower performs second distillation on the third gas and third liquid phases to obtain crude helium and a fourth liquid phase form which nitrogen is removed by the nitrogen removal tower.

Abstract: The integrated automated cell culture device includes a main body, a cover, a connection seat, a gas module, a temperature module, at least one slide track, and a clamping member. The main body encloses a culture room for receiving a culture bag. The cover is disposed on the opening of the culture room. The connection seat is received in a receiving slot of the main body and is adapted for a pipe to penetrate. The gas module detects the carbon dioxide's concentration and selectively injects gas into the culture room. The temperature module detects the temperature in the culture room and selectively heats the culture room. The slide track is disposed on the bottom of the culture room. The clamping member is slidably disposed on the slide track and clamps the culture bag to make the fluid in the culture bag move to one side of the culture bag.

Abstract: A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.

Abstract: A semiconductor device includes an interposer, a first die, a second die, a third die and a dummy die. The interposer includes a first region and a second region. The first die and the second die are bonded to a first surface of the interposer, the first die is disposed in the first region, and the second die is disposed in the second region. The third die and the dummy die are bonded to a second surface opposite to the first surface of the interposer, wherein the third die is disposed in the first region and the dummy die is disposed in the second region.