Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A voltage stabilizer is provided for stabilizing a gate-source voltage of a switching element, wherein a source of the switching element receives a first driving voltage. The voltage stabilizer includes a transistor and a first resistor. A base of the transistor receives a second driving voltage, a collector of the bipolar junction transistor is electrically connected to a gate of the switching element, a first terminal of the first resistor is electrically connected to the collector and the gate, a second terminal of the first resistor is electrically connected to the source of the switching element and receives the first driving voltage.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: An active noise cancelling cord contains: a plug including a ground-wire conductor, a live-wire conductor, and a neutral-wire conductor; a socket including a protrusion in which a first receiving orifice, a second receiving orifice and a third receiving orifice are defined; and a noise reduction mode. The body is connected with a plug and a socket, and a shell is located between the plug and the socket. The conductive set includes a ground wire electrically connected with a ground-wire conductor and a first receiving orifice, a live wire electrically connected with a live-wire conductor and a second receiving orifice, a neutral wire electrically connected with a neutral-wire conductor and a third receiving orifice, a plug anti-noise wire electrically connected with a live-wire conductor, and the noise reduction mode, and a socket anti-noise wire electrically connected with the second receiving orifice and the noise reduction mode.

Abstract: A resveratrol composition and its preparation method and application are disclosed, which relates to the technical field of resveratrol solid dispersion preparation. A resveratrol composition is prepared from following raw materials: 6%-60% by weight of resveratrol, and 40%-94% by weight of poloxamer. The disclosure mixes the resveratrol and poloxamer in proportion to prepare a composition, and further improves the dissolution and bioavailability of the resveratrol in combination with microencapsulation technology. The preparation process is suitable for industrialization and has good application and promotion prospects.

Abstract: Exemplary embodiments for redistribution layers of integrated circuits are disclosed. The redistribution layers of integrated circuits of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

Abstract: A power detection circuit is provided for detecting current total input power of a resonant circuit. The power detection circuit includes a detection circuit and an estimation circuit. The detection circuit receives a current signal and obtains resonant-slot baseband power according to the current signal to generate the baseband power value. The current signal represents a resonant-slot current generated by the resonant circuit. The estimation circuit receives the baseband power value and estimates the current total input power according to the baseband power value to generate an estimated power value.

Abstract: An embodiment semiconductor package assembly may include an interposer, an integrated passive device electrically coupled to a first side of the interposer, an underfill material portion formed between the integrated passive device and the first side of the interposer, and a dam protruding from the first side of the interposer and configured to constrain a spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer that also includes a component of a redistribution interconnect structure. The dam further be electrically isolated from the redistribution interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.

Abstract: In a method of manufacturing a semiconductor device, a trench pattern is formed in a first layer disposed over an underlying layer, and a first dimension of the trench pattern is reduced by first directional deposition. In the first directional deposition, a deposition rate on a first side wall of the trench pattern extending in a first axis is greater than a deposition rate on a second side wall of the trench pattern extending in a second axis crossing the first axis, the first axis and the second axis being horizontal and parallel to a surface of the underlying layer.

Abstract: Method and apparatus of coding pictures containing one or more virtual boundaries, such as 360-degree virtual reality (VR360) video are disclosed. According to this method, a reconstructed filtered unit associated with a loop filter for a current reconstructed pixel is received. The loop filtering process associated with the loop filter is applied to the current reconstructed pixel to generate a filtered reconstructed pixel, where if the loop filtering process for the current reconstructed pixel is across a virtual boundary of the picture, the loop filtering process is disabled when fixed-size loop filtering is used or a smaller-size loop filter is selected when adaptive-size loop filtering is used for the current reconstructed pixel, where the filtered reconstructed pixel is the same as the current reconstructed pixel when the loop filtering process is disabled. The filtered reconstructed pixel is the same as the current reconstructed pixel.

Abstract: A water replenishment device includes a water generator and a container. The water generator includes a seat body, a heat exchanger, and a thermoelectric cooler. The seat body has a fluid channel and a catchment hole. The catchment hole is in fluid communication with the fluid channel, and the fluid channel is configured for an environment airflow to pass therethrough. The heat exchanger is partially located in the fluid channel. The thermoelectric cooler has a cold surface and a hot surface. The cold surface of the thermoelectric cooler is thermally coupled to the heat exchanger. The container has a storage space. The storage space is in fluid communication with the fluid channel via the catchment hole. The thermoelectric cooler is configured to condense the environment airflow to a liquid, and the liquid is configured to be stored in the storage space via the catchment hole.

Abstract: In a mobile cellular network, a mobile network operator (MNO) or other entity can specify whether a user equipment (UE) is to utilize either a concealed identifier (e.g., a subscription concealed identifier (SUCI)) calculated by a universal subscriber identity module (USIM) of a universal integrated circuit card (UICC) or a concealed identifier calculated by mobile equipment (ME) of the UE that is separate from the UICC and USIM. In the event that a USIM-calculated concealed identifier is specified for use but the USIM fails in generation of a concealed identifier, the UE can utilize one or more failure recovery procedures to attempt completion of attachment of the UE to the same network or a different network to help ensure that the UE does not remain attached to a network without access to services of the network due to authentication failure.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine multiple voltage values associated with a rechargeable battery over a period of time; store the multiple voltage values with respect to multiple clock values over the period of time; determine a voltage drop rate from the multiple voltage values and the multiple clock values; determine a threshold voltage value associated with a predicted energy capacity of the rechargeable battery for a mobile information handling system (IHS) to perform a power state transition; determine a voltage value associated with the rechargeable battery; determine that the voltage value has reached the threshold voltage value; provide a notification to an operating system executed by the mobile IHS; store data from a volatile memory medium to a non-volatile memory medium; and transition the mobile IHS from an operational state to a power conservation state.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: An oscillation circuit including an amplifier, a feedback resistor and a first switch circuit is provided. The amplifier inverts and amplifies an oscillation signal received from an input terminal thereof to provide an output oscillation signal at an output terminal thereof. The feedback resistor is coupled between the input terminal and the output terminal, and coupled with the first switch circuit in parallel. The first switch circuit conducts the input terminal to the output terminal in one of the following situations: (1) an input voltage of the oscillation signal is higher than an output voltage of the output oscillation signal by at least a first threshold value; and (2) the output voltage is higher than the input voltage by at least a second threshold value. The first switch circuit has a first on-state resistance smaller than a resistance of the feedback resistor.