Abstract: A method for sending system information includes: sending, by a network side, first system information to a terminal, in which the first system information includes first information of a group of second system information, and the first information includes one or a combination of: a control information aggregation level of the second system information, a number of MIMO layers of the second system information, a valid area of the second system information, valid time of the second system information, receiving condition information of the second system information, an MCS index indicating a modulation and coding scheme of a PDCCH or a PDSCH of the second system information, a modulation mode of the second system information, a subcarrier spacing for sending the second system information, and the like; and sending, by the network side, the group of second system information to the terminal based on the first information.

Abstract: A plant growing lamp includes a lamp body, a power supply, and a fixing device, the fixing device includes an upper clip body and a lower clip body; the upper clip body is hollow; one end of the lamp body is inserted from the upper clip body and is fixed; and the power supply is electrically connected to the lamp body. By the arrangement of the above structure, the lamp body, the upper clip body, and the lower clip body can be produced separately during use, which is convenient for standardized production and assembling. The lamp body is stably mounted at a suitable position through the fixing device, and the power supply is electrically connected to the lamp body, so that the entire lamp can provide a stable and continuous lighting service for a specific environment to meet lighting needs of different plants.

Abstract: Provided are a device and method for human parsing. The method includes receiving at least one piece of image data and ground truth values for human parsing, generating a height distribution map and a width distribution map for the image data, acquiring attention maps and scaled feature maps for each of a height and a width of the image data using the distribution maps, calculating a distribution loss rate by concatenating the scaled feature maps, acquiring an improved feature map on the basis of the calculated distribution loss rate, and performing human parsing on an object included in the image data using the improved feature map.

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: Provided is a fusion protein containing GLP-1 and FGF21 linked through an immunoglobulin Fc portion. Each of the GLP-1 and FGF21 can be substituted with its analogues or variants and, the Fc portion, which can be derived from IgG4, can include substitutions that further enhance the fusion protein's stability and activity. These fragments can be linked together through peptide linkers. The fusion protein can be used clinically to reduce glucose and lipid levels and body weight.

Abstract: A semiconductor device comprises: a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has: a p-type buried layer; and a junction field effect region in contact with the p-type buried layer in a gate region. The semiconductor device further comprises: a gate oxide layer on the silicon carbide epitaxial layer; a poly silicon layer on the gate oxide layer; an interlayer dielectric layer on the poly silicon layer; a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate including a semiconductor substrate and an insulator layer over the semiconductor substrate; forming a trench through the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench and over an upper surface of the second region; thickening the initial epitaxial layer to form an epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: Disclosed in the present application are an information reporting method, a terminal device, and a network side device. The method comprises: a terminal device acquiring or recording related information during data transmission in a radio resource control (RRC) inactive state; and reporting the related information to a network side device.

Abstract: A semiconductor device includes a gate structure, an insulating layer and two source/drain regions. A portion of the gate structure is embedded in a substrate. The insulating layer is disposed between the portion of the gate structure and the substrate and encompasses the portion of the gate structure. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: Devices and methods include generating biases for input buffers of a semiconductor device. In some embodiments, the semiconductor device includes an input buffer that buffer datas and biasing generation and distribution circuitry that generates and distributes a bias current to the input buffer based at least in part on a reference voltage. The biasing generation and distribution circuitry includes dynamic voltage bias circuitry that adjusts the bias current and reference voltage tracking circuitry that controls operation of the dynamic voltage bias circuitry based on the reference voltage.

Abstract: A touch module includes first and second mesh electrode layers respectively with first and second irregular mesh patterns. Line segments of the first irregular mesh pattern are configured to form a first radial pattern having a first intersection point by translation. A top X % fan-blade shape area of line segment density in the first radial pattern is defined as a first dense area, in which X is at least 10. Line segments of the second irregular mesh pattern are configured to form a second radial pattern having a second intersection point by translation. A top X % fan-blade shape area of line segment density in the second radial pattern is defined as a second dense area. When the first radial pattern and the second radial pattern are translated so that the first and second intersection points coincide, the first dense area and the second dense area do not overlap.

Abstract: A multi-layer printed circuit board includes a base-layer metal, multiple middle metal layers and a top-layer metal. The middle metal layers are stacked on the base-layer metal sequentially. The top-layer metal is disposed on the middle metal layers. The base-layer metal, each middle metal layer and the top-layer metal are formed with multiple through holes respectively. Part of the middle metal layers are separately formed with multiple hole groups corresponding to the through holes. Each hole group includes multiple passing holes. The passing holes jointly surround a corresponding one of the through holes to form multiple connecting channels. Therefore, the multi-layer printed circuit board may reduce the cooling speed of the through holes to avoid an excessively low temperature of a pad to affect the soldering efficiency with keeping the high-frequency transmission and the signal isolation.

Abstract: A holding device for a top-opening substrate container includes a holding assembly for pushing a substrate actuator disposed at a substrate to operate. The holding assembly includes a holding body and a pushing actuator. The pushing actuator includes a first guiding sloped surface for pressing against a second guiding sloped surface of an inner surface of a container door structure. The first guiding sloped surface causing corresponding pushing and displacement between the first guiding sloped surface and the second guiding sloped surface according to a supporting force of the container door structure. A pushing section is connected to the first guiding sloped surface, and capable of correspondingly pushing the substrate actuator to operate according to a level of the pushing and displacement of the first guiding sloped surface, such that the substrate actuator displaces substrates and stacks the substrates with another in layers.

Abstract: A semiconductor device and methods for manufacturing the same are provided. The semiconductor device includes a substrate, a NFET structure on the substrate, and a PFET structure on the substrate. The NFET structure includes a first source region, a first drain region and a first gate structure between the first source region and the first drain region. The first gate structure includes a first high-k dielectric layer and a first gate layer on the first high-k dielectric layer. The PFET structure includes a second source region, a second drain region and a second gate structure between the second source region and the second drain region. The second gate structure includes a second high-k dielectric layer and a second gate layer on the second high-k dielectric layer. A thickness of the first high-k dielectric layer is larger than a thickness of the second high-k dielectric layer.

Abstract: Systems, devices, and methods for dermal treatments are provided. Various systems, devices, and methods provide treatment options with a handheld device, intradermal or subdermal fluid delivery via a needle or microneedle. For fluid delivery, system can include an injector, fluid-filled container, and a needle or hollowed microneedle. A fluid-filled container can be compatibly coupled with a treatment device such to perform the various dermal treatments. Further, fluid delivery systems can be utilized in a number of applications, including medications and supplements for the skin.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: The present application provides an information processing method and related devices. The information processing method includes: performing, by a terminal, a first operation; wherein the first operation includes at least one of the following: transmitting first information to a first base station; wherein the first information is used to indicate first status information of a QoE configuration, and the first status information of the QoE configuration is current status information of a QoE configuration which the terminal is in; receiving second information transmitted by a second base station; wherein the second information is used to indicate second status information of a QoE configuration, and the second status information of the QoE configuration is status information of a QoE configuration indicated by the second base station for the terminal to be in. The first base station and the second base station are the same base stations or different base stations.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.