Abstract: An image convolution accelerator system including processing elements having kernel elements corresponding to a generated Toeplitz-like kernel. The Toeplitz-like generated kernel is based on a desired convolution kernel and padded with zeros, and an image controller is configured to activate the processing elements to multiply the kernel elements with image data when image data from a same row of the image is allocated to all processing elements corresponding to a non-zero row of the Toeplitz-like kernel. At least one storage element is configured to store at least the number of columns of the image minus a dimension of the desired convolution kernel+1.

Abstract: The present disclosure provides a random access method, a UE and a network side device. The random access method includes: initiating random access on one or more SS blocks; and sending random access information on each SS block to the network side device.

Abstract: An ultrasonic-assisted heat press machine, includes a frame, a material tank, an extruder, an ultrasonic wave generator, and a heater. The material tank is disposed on the frame and includes a cavity for accommodating an oil-bearing raw material. The extruder is extended in the cavity. The ultrasonic wave generator is disposed on the frame and adjacent to the material tank. The heater is disposed on the frame and adjacent to the material tank. The heater is configured to produce heat to heat the cavity and the ultrasonic wave generator, and regulate the working frequency of the ultrasonic wave generator. When in use, the heater, the extruder, and the ultrasonic wave generator cooperate to separate oil from the oil-bearing raw material in the material tank.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first semiconductor layer, including a first trench isolation that extends through a portion of the first substrate layer; and a first interconnect structure, disposed over the first semiconductor layer. The second substrate includes a second semiconductor layer, including a plurality of semiconductor islands and surrounded by at least a second isolation penetrating the second semiconductor layer; a second interconnect structure, disposed over the second substrate layer and bonded to the first interconnect structure; and a dielectric layer, disposed over the second semiconductor layer opposite to the second interconnect structure. A method of manufacturing the semiconductor structure is also provided.

Abstract: An image processing method including allocating a plurality of memory banks. Each memory bank includes a plurality of memory bank rows. The image is divided into a plurality of tags, wherein each tag has tag rows, each tag row has a plurality of pixels, and each tag row is consecutively distributed over different memory banks such that each tag row of the tag is accessible to be read out from the memory banks simultaneously. The consecutive distribution of the tag rows is performed by distributing the tag rows (r) in order starting from a first tag row (r) and to the memory banks (b) in order starting at the first memory bank (b), until all tag rows (r) have been distributed.

Abstract: A silicon wafer, a preparation method of the silicon wafer, and a passivation treatment solution is disclosed. The preparation method of the silicon wafer can include the following steps: providing a solar silicon ingot; cutting the solar silicon ingot with a first treatment solution to form a pretreated silicon wafer; degluing the pretreated silicon wafer with a second treatment solution to obtain a deglued silicon wafer; and cleaning the deglued silicon wafer with a third treatment solution to obtain the silicon wafer; wherein at least one of the first treatment solution, the second treatment solution and the third treatment solution comprises a non-metallic compound that is bonded with a silicon ion via a single bond.

Abstract: A method for treating a semiconductor structure includes: forming the semiconductor structure which includes a carrier substrate, a device substrate, a semiconductor device formed on the device substrate, and a bonding layer formed to bond the semiconductor device with the carrier substrate, the device substrate having an upper surface which is faced upwardly, and which is opposite to the semiconductor device; and directing a chemical fluid to impinge the upper surface of the device substrate so as to remove an edge portion of the device substrate.

Abstract: A femoral lift apparatus includes a lift device and a hook device. The hook device is coupled to the lift device. The femoral lift apparatus is labor-saving and can avoid the problem that the conventional femoral lift apparatus may block the surgical view, hinder the operation position for a hip joint replacement surgery. With the assistance of this current femoral lift apparatus, the hip joint replacement surgery can be performed more smoothly.

Abstract: Devices and methods include generating biases for input buffers of a semiconductor device. In some embodiments, the semiconductor device includes an input buffer that buffer datas and biasing generation and distribution circuitry that generates and distributes a bias current to the input buffer based at least in part on a reference voltage. The biasing generation and distribution circuitry includes dynamic voltage bias circuitry that adjusts the bias current and reference voltage tracking circuitry that controls operation of the dynamic voltage bias circuitry based on the reference voltage.

Abstract: The invention belongs to the technical field of current detection, in particular to a fluxgate current sensor and a current measurement method, wherein the fluxgate current sensor comprises a magnetic probe and an excitation and detection circuit, and the magnetic probe comprises an excitation iron core and an excitation coil, the excitation coil is connected to the excitation and detection circuit, the excitation and detection circuit is used to output alternating excitation voltages to the excitation coil, and the excitation coil is excited to generate alternating excitation currents and cause the excitation iron core to reach saturation alternately; the excitation and detection circuit is further configured to convert the excitation currents flowing through the excitation coil, into equivalent differences of two currents, so as to calculate average values of the excitation currents flowing through the excitation coil via differential equivalent currents, thereby calculating to-be-measured primary currents

Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Abstract: The present invention relates to a method and apparatus for controlling a wind turbine. The method includes: dividing a plurality of wind turbines into at least one group based on a similarity in status information of the plurality of wind turbines; in response to having detected a fault in a first wind turbine of the plurality of wind turbines, searching a group to which the first wind turbine belongs for a second wind turbine matching status information of the first wind turbine; and controlling the first wind turbine based on parameters from the second wind turbine.

Abstract: The present invention relates to a composition for raising an immune response in an animal which prevents or decreases the risk of a coronavirus infection and decreases severity of disease. In particular, the invention relates to vaccines and/or immunogenic compositions for raising an immune response in an animal which prevents or decreases the risk of the SARS-CoV-2 disease named COVID-19 by the World Health Organization. The composition comprises an attenuated poxvirus, and especially a vaccinia virus, wherein the attenuated poxvirus genome comprises a coronavirus SARS-CoV-2 nucleic acid sequence encoding the spike protein polypeptide and or the membrane protein polypeptide and or nucleocapsid protein polypeptide and or envelope protein polypeptide or an immunogenic or functional part of any of these.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

Abstract: A humanized antibody or antigen-binding fragment thereof capable of specifically recognizing TrkA and uses thereof. The antibody includes a heavy chain variable region with an amino acid sequence shown in any one of SEQ ID NO: 2-8, and a light chain variable region with an amino acid sequence shown in any one of SEQ ID NO: 10-13. The above-mentioned antibody according to the embodiments of the present invention can specifically target and bind to the TrkA receptor and block the binding of NGF and TrkA.

Abstract: A screening method of individualized tumor neoantigen peptide and a vaccine preparation thereof are provided. The screening method includes: Step 1, collecting and collating variable information for mutation producing a neoantigen and an antigenic peptide; Step 2, calculating according to a formula to obtain a score of each antigenic peptide; Step 3, arranging the antigen peptides in a descending order according to iNeo_Score, and selecting the antigen peptides from top to bottom successively; Step 4, continuing to select an antigenic peptide until enough candidate antigenic peptides are obtained or all of candidate antigenic peptides are selected so as to obtain screened antigenic peptides; and Step 5, grouping the screened antigen peptides into preparation groups. The designed individualized tumor neoantigen peptide is screened and prepared into a preparation in the disclosure, which includes screened antigen peptide, inorganic salt and an excipient. The preparation can be made into small-volume injection.