Patents by Inventor Liang-Pin Tai

Liang-Pin Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8724349
    Abstract: An apparatus and method for output voltage calibration of a primary feedback flyback power module extract the difference between the output voltage of the power module and a target value, and according thereto, calibrate a reference voltage which is used in regulation of the output voltage, to thereby calibrate the output voltage to be the target value.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 13, 2014
    Assignee: Richtek Technology Corp.
    Inventors: Chien-Fu Tang, Isaac Y. Chen, Liang-Pin Tai
  • Publication number: 20130229833
    Abstract: A feedback circuit for an isolated power converter includes an opto-coupler and a reversed polarity regulator. The opto-coupler provides a current related to an output voltage of the isolated power converter. When the isolated power converter enters light load, the output voltage rises and the reversed polarity regulator reduces the current to decrease the power consumption and thus improve the light load efficiency of the isolated power converter.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: Liang-Pin TAI, Tzu-Chen LIN, Cheng-Hsuan FAN
  • Patent number: 8503196
    Abstract: A feedback circuit for an isolated power converter includes an opto-coupler and a reversed polarity regulator. The opto-coupler provides a current related to an output voltage of the isolated power converter. When the isolated power converter enters light load, the output voltage rises and the reversed polarity regulator reduces the current to decrease the power consumption and thus improve the light load efficiency of the isolated power converter.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 6, 2013
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Tzu-Chen Lin, Cheng-Hsuan Fan
  • Patent number: 8169206
    Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 1, 2012
    Assignee: Richtek Technology Corp.
    Inventors: Tsai-Fu Chang, Liang-Pin Tai
  • Publication number: 20120008345
    Abstract: An apparatus and method for output voltage calibration of a primary feedback flyback power module extract the difference between the output voltage of the power module and a target value, and according thereto, calibrate a reference voltage which is used in regulation of the output voltage, to thereby calibrate the output voltage to be the target value.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 12, 2012
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: CHIEN-FU TANG, ISAAC Y. CHEN, LIANG-PIN TAI
  • Patent number: 8063617
    Abstract: A per-phase quick response generation circuit generates a quick response signal to determine a quick response pulse to be inserted into a pulse width modulation signal of the corresponding phase. The quick response pulse will force the upper power switch of the corresponding phase on to increase the current supply ability during load transition. A multi-phase voltage regulator with the quick response generation circuit can have different quick response pulse widths for the interleaved phases, so as to decrease the current imbalance period of the voltage regulator after load transition.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: November 22, 2011
    Assignee: Richtek Technology Corp.
    Inventors: Ting-Hung Wang, Chia-Jung Lee, Liang-Pin Tai
  • Patent number: 8040122
    Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: October 18, 2011
    Assignee: Richtek Technology Corp.
    Inventors: Tsai-Fu Chang, Liang-Pin Tai
  • Patent number: 8031493
    Abstract: A method and apparatus are provided for a switching mode converter to improve the light load efficiency thereof. The converter is thus operated with three modes by monitoring a feedback signal and a supply voltage. When the feedback signal indicates that loading gets light enough, the converter is switched from the first mode to the second mode, and during the second mode some cycles are skipped. If loading is too light, the converter is switched from the second mode to the third mode, and during the third mode more cycles will be skipped.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: October 4, 2011
    Assignee: Richtek Technology Corp.
    Inventors: Pei-Lun Huang, Liang-Pin Tai
  • Publication number: 20110068763
    Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 24, 2011
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: TSAI-FU CHANG, LIANG-PIN TAI
  • Publication number: 20110018590
    Abstract: A feedback circuit for an isolated power converter includes an opto-coupler and a reversed polarity regulator. The opto-coupler provides a current related to an output voltage of the isolated power converter. When the isolated power converter enters light load, the output voltage rises and the reversed polarity regulator reduces the current to decrease the power consumption and thus improve the light load efficiency of the isolated power converter.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 27, 2011
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: LIANG-PIN TAI, TZU-CHEN LIN, CHENG-HSUAN FAN
  • Patent number: 7838901
    Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: November 23, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jing-Meng Liu, Hung-Der Su
  • Patent number: 7838900
    Abstract: A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: November 23, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jing-Meng Liu, Hung-Der Su
  • Patent number: 7838902
    Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: November 23, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jing-Meng Liu, Hung-Der Su
  • Patent number: 7834606
    Abstract: A control circuit provides a control signal for a constant on-time PWM switching converter to produce an output voltage, such that the converter operates with a constant on-time at a first state and operates with a variable on-time at a second state, so as to decrease the switching frequency and thereby the switching loss, to increase the efficiency of the converter, to improve the transient response, and to reduce the recovery time of the output voltage.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: November 16, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Kuo-Ping Liu, Ko-Cheng Wang, Liang-Pin Tai, Chung-Sheng Cheng
  • Patent number: 7786604
    Abstract: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second leadframe, and several pins electrically connected to the leadframes and source and gate regions. The second leadframe is electrically connected to the first source region. The pins connected to the first leadframe and second source region are on a side of the package, and the pins connected to the first gate region, second leadframe, and second gate region are on another side of the package.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: August 31, 2010
    Assignee: Richtek Technology Corp.
    Inventor: Liang-Pin Tai
  • Patent number: 7781921
    Abstract: The subject matter is a voltage regulator capable of providing an indicator signal to a load, so that the load can operation under the best current-voltage relationship according to the indicator signal. To this end, the voltage regulator includes an amplifier for generating the indicator signal by amplifying a difference between a signal representative of an output voltage and a signal representative of a reference voltage.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 24, 2010
    Assignee: Richtek Technology Corporation
    Inventors: Chien-Hui Wang, Jian-Rong Huang, Kuo-Lung Tseng, Liang-Pin Tai
  • Patent number: 7768033
    Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 3, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jing-Meng Liu, Hung-Der Su
  • Patent number: 7759695
    Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 20, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Liang-Pin Tai, Jing-Meng Liu, Hung-Der Su
  • Patent number: 7701190
    Abstract: For a DC-to-DC converter including a plurality of channels for converting an input voltage to an output voltage, a control circuit comprises a load transient detector to detect the output voltage to provide a quick response signal. In a load transient, the quick response signal triggers a quick transient response period to increase the operational frequency of the converter.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: April 20, 2010
    Assignee: Richtek Technology Corp.
    Inventors: Jiun-Chiang Chen, Liang-Pin Tai
  • Patent number: 7696731
    Abstract: The present invention discloses a method and a circuit for reducing switching ringing in a switching regulator. The switching regulator comprises two transistors, and the two transistors are never simultaneously OFF. A phase lock loop may be provided to fix the output signal frequency of a PWM control circuit to a set frequency.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: April 13, 2010
    Assignee: Richtek Technology Corporation
    Inventors: Jian-Rong Huang, Kuo-Lung Tseng, Liang Pin Tai