Patents by Inventor Liang Shao

Liang Shao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THINNING PROCESS USING METAL-ASSISTED CHEMICAL ETCHING
    Publication number: 20180012880
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
    Publication number: 20170373050
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first semiconductor device to a second semiconductor device by spacers. The first semiconductor device has first contact pads disposed thereon, and the second semiconductor device has second contact pads disposed thereon. The method includes forming an immersion interconnection between the first contact pads of the first semiconductor device and the second contact pads of the second semiconductor device.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Tung-Liang Shao, Yi-Li Hsiao, Hsiao-Yun Chen, Chih-Hang Tung, Chen-Hua Yu
  • System and Method for Immersion Bonding
    Publication number: 20170330855
    Abstract: A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Chih-Hang Tung, Su-Chun Yang, Tung-Liang Shao, Chen-Hua Yu
  • Hollow metal pillar packaging scheme
    Patent number: 9812434
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9786591
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Hollow Metal Pillar Packaging Scheme
    Publication number: 20170271316
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Multi-Strike Process for Bonding
    Publication number: 20170194278
    Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
    Type: Application
    Filed: February 15, 2017
    Publication date: July 6, 2017
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
  • Fixing screw structure for adjusting a fixing procedure
    Patent number: 9677584
    Abstract: A fixing screw structure for adjusting a fixing procedure used for fixing a panel to a casing, including a screw, an elastomer and a fixing frame. The screw includes a threaded portion and a tapered portion, and passes through the panel, and the threaded portion is screwed on the casing. The elastomer is annular and disposed around the screw, and has a taper hole corresponding to the tapered portion. The fixing frame is a hollow tube, and is fixed on the panel and positioned around the elastomer. When the screw is screwed, the tapered portion abuts the inner wall of the taper hole and the elastomer is expanded outwardly to fitly abut the inner wall of the fixing frame. The instant disclosure transforms the longitudinal screwing force into a transverse expanding force to fix the panel, thereby eliminating the cumulative tolerance of the casing and the panel.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: June 13, 2017
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Hou-An Su, Yu-Liang Shao
  • Hollow metal pillar packaging scheme
    Patent number: 9679883
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Metal insulator metal capacitor and method for making the same
    Patent number: 9673270
    Abstract: A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Tung-Liang Shao, Ching-Jung Yang
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170154881
    Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The method for manufacturing a semiconductor device includes: attaching a carrier wafer to a front side of a top die wafer; thinning a back side of the top die wafer, the back side of the top die wafer being opposite to the front side the top die wafer; singulating the carrier wafer and the top die wafer whereby singulated dies attached to singulated carrier dies are formed; and bonding back side of each of the singulated dies to a front side of a bottom die wafer.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: TUNG-LIANG SHAO, CHIH-HANG TUNG, CHEN-HUA YU
  • Package with Solder Regions Aligned to Recesses
    Publication number: 20170141054
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Multi-strike process for bonding
    Patent number: 9576929
    Abstract: A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Wen-Lin Shih, Hsiao-Yun Chen, Chen-Hua Yu
  • Capacitor in Post-Passivation Structures and Methods of Forming the Same
    Publication number: 20170040256
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • REMOVAL ASSEMBLY
    Publication number: 20170042054
    Abstract: A removal assembly includes a main body, a positioning element, an elastic element, an actuating element, and a wrench element. The positioning element is movably disposed in an inner space of the main body, including a clasp part and an oblique side surface, and the clasp part extends out of the main body. The elastic element is disposed between the main body and the positioning element. The actuating element is pivotally installed in the inner space of the main body, including a pressing part and an abutting part, the pressing part extends out of the main body, and the abutting part abuts against the oblique side surface of the positioning element. The wrench element is connected to the main body, including a fixing part and a pivoting part.
    Type: Application
    Filed: December 17, 2015
    Publication date: February 9, 2017
    Inventors: HOU-AN SU, YU-LIANG SHAO
  • Package with solder regions aligned to recesses
    Patent number: 9559044
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • FIXING SCREW STRUCTURE FOR ADJUSTING A FIXING PROCEDURE
    Publication number: 20170023037
    Abstract: A fixing screw structure for adjusting a fixing procedure used for fixing a panel to a casing, including a screw, an elastomer and a fixing frame. The screw includes a threaded portion and a tapered portion, and passes through the panel, and the threaded portion is screwed on the casing. The elastomer is annular and disposed around the screw, and has a taper hole corresponding to the tapered portion. The fixing frame is a hollow tube, and is fixed on the panel and positioned around the elastomer. When the screw is screwed, the tapered portion abuts the inner wall of the taper hole and the elastomer is expanded outwardly to fitly abut the inner wall of the fixing frame. The instant disclosure transforms the longitudinal screwing force into a transverse expanding force to fix the panel, thereby eliminating the cumulative tolerance of the casing and the panel.
    Type: Application
    Filed: October 21, 2015
    Publication date: January 26, 2017
    Inventors: HOU-AN SU, YU-LIANG SHAO
  • Thermally enhanced structure for multi-chip device
    Patent number: 9530715
    Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20160372434
    Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.
    Type: Application
    Filed: September 6, 2016
    Publication date: December 22, 2016
    Inventors: TUNG-LIANG SHAO, YU-CHIA LAI, HSIEN-MING TU, CHANG-PIN HUANG, CHING-JUNG YANG
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9490203
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen