Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

Abstract: An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

Abstract: There are disclosed antenna arrays for portable electronic devices. In one aspect, the antenna array comprises at least two antennas, each antenna comprising at least two radiating elements; and at least two control networks each comprising a plurality of impedance matching circuits and RF switches, each antenna being connected to a respective control network. Each control network connects the radiating elements of its respective antenna to a single RF port. Each antenna element is connected to a respective first RF switch in its respective control network allowing selection between different ones of the plurality of impedance matching circuits. Each port is connected to a respective second RF switch in its respective control network allowing selection between different ones of the plurality of impedance matching circuits. The impedance matching circuits are connected between the first RF switches and the second RF switch in each control network.

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

Abstract: The invention relates to the technical field of pump truck control, and discloses a pump truck boom control method, a pump truck boom control system and a pump truck. The pump truck boom control method comprises: detecting a working condition of a boom, wherein the boom is divided into first-type arms close to the first arm and second-type arms close to the last arm in advance; and controlling each arm in the first-type arms to act at respective preset movement speed when the boom is in an opening placing boom working condition before the construction or in a folding placing boom working condition after the construction. The method can realize speed-up control on movement speeds of the each arm in the first-type arms under the opening placing boom working condition before the construction or under the folding placing boom working condition after the construction without a boom posture detection sensors.

Abstract: There is disclosed an antenna arrangement for a portable electronic device. The antenna arrangement comprises a conductive ground plane having an edge and a substantially rectangular recess formed in the edge of the ground plane. The recess has a base, an open edge opposed to the base, and at least a first side extending from the base. A first conductor element extends across the open edge of the recess, a first end of the first conductor element being connected to the ground plane at the first side of the recess. The first conductor element leaves at least one gap at the edge of the recess, such that the first conductor element, the first side of the recess and the base of the recess together define a slot in the ground plane and the at least one gap defines at least one notch in the slot. A second conductor element is disposed within the recess and connected to or configured to couple with the ground plane.

Abstract: A semiconductor package includes a die attach pad and a plurality of leads, and a die attached to the die attach pad and electrically coupled to the plurality of leads. The plurality of leads includes power leads and signal leads. An interconnecting trace is electrically coupled between a bond pad of the die and a via-pad. A via is coupled to the via-pad, and the via pad is coupled to one of the signal leads. A bypass trace includes a proximal end connected to the interconnecting trace and a distal end floating inside a mold compound of the semiconductor package.

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

Abstract: A housing for an electronic device includes a metal member combined with a plastic member. The combination molds the metal member to the plastic member but the plastic member is discontinuous and recesses and protrusions are cut into the metal member to enable molding and bonding with the plastic member in the manner of a dovetail joint. Manufacture in this way increases bonding strength and reduces the likelihood of internal stresses in the cooling plastic member resulting from complete envelopment of the metal by the plastic. The metal member and the plastic member are thus integrally formed and a thickness of a recess is less than a thickness of the plastic member. An electronic device and a method for making the housing are also provided.

Abstract: There are disclosed antenna arrays for portable electronic devices. In one aspect, the antenna array comprises at least two antennas, each antenna comprising at least two radiating elements; and at least two control networks each comprising a plurality of impedance matching circuits and RF switches, each antenna being connected to a respective control network. Each control network connects the radiating elements of its respective antenna to a single RF port. Each antenna element is connected to a respective first RF switch in its respective control network allowing selection between different ones of the plurality of impedance matching circuits. Each port is connected to a respective second RF switch in its respective control network allowing selection between different ones of the plurality of impedance matching circuits. The impedance matching circuits are connected between the first RF switches and the second RF switch in each control network.

Abstract: There is disclosed an antenna arrangement for a portable electronic device. The antenna arrangement comprises a conductive ground plane having an edge and a substantially rectangular recess formed in the edge of the ground plane. The recess has a base, an open edge opposed to the base, and at least a first side extending from the base. A first conductor element extends across the open edge of the recess, a first end of the first conductor element being connected to the ground plane at the first side of the recess. The first conductor element leaves at least one gap at the edge of the recess, such that the first conductor element, the first side of the recess and the base of the recess together define a slot in the ground plane and the at least one gap defines at least one notch in the slot. A second conductor element is disposed within the recess and connected to or configured to couple with the ground plane.