Abstract: The invention is directed to a method for manufacturing a semiconductor device. The method comprises steps of forming a gate dielectric layer, a polysilicon layer and a patterned cap layer over a substrate sequentially and patterning the polysilicon layer to be a polysilicon gate by using the patterned cap layer as a mask. A plurality of lightly doped drain (LDD) regions are formed in the substrate aside the polysilicon gate, wherein a channel region is formed between the LDD regions in the substrate. A spacer is formed on the sidewall of the polysilicon gate and a source/drain region is formed in the substrate adjacent to the spacer. The patterned cap layer is removed and the spacer is removed. A metal silicidation process is performed for transforming the polysilicon gate into a metal silicide gate and forming a metal silicide layer at a surface of the source/drain region.

Abstract: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.