Patents by Inventor Liang-Yi Chen

Liang-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266662
    Abstract: A wireless charging device of game machines, which comprises a game machine, provided with at least a table top, and the table top is provided with at least a concave tray; at least a wireless charging device, located in the concave tray of the table top; there is a panel at the top of the table top of the game machine, and the panel covers the wireless charging device in the tray; the wireless charging device comprises a wireless charging part and a charging support connected to each other. Thereby, the 3C product can be charged without a USB cable, it can be directly placed on the table top with a wireless charging device of game machine for wireless charging.
    Type: Application
    Filed: February 2, 2020
    Publication date: August 20, 2020
    Inventors: Nien-Chang HUANG, Yun-Ping CHEN, Yu-Chia HUNG, Hao-En HUNG, Po-Wen LU, Liang-Yi HO
  • Publication number: 20200194951
    Abstract: An endoscope device and a cable assembly thereof are provided. The cable assembly includes a first substrate, a second substrate, and a wire. The first substrate includes a first body and a first solder pad disposed on the first body. The second substrate is correspondingly disposed on the first substrate and includes a second body, a second solder pad disposed on the second body and corresponding to the first solder pad, and an accommodating portion corresponding to the second solder pad. The wire includes a soldering portion disposed in the accommodating portion. The first solder pad and the second solder pad are coupled to each other by at least one of a first solder and a second solder, and the soldering portion and the second solder pad are coupled to each other by the first solder.
    Type: Application
    Filed: September 2, 2019
    Publication date: June 18, 2020
    Inventors: HSI-HSIN LOO, PARN-FAR CHEN, LIANG-YI LI, CHAO-YU CHOU
  • Patent number: 10575664
    Abstract: An article for mounting to a vertical surface comprising a substrate having a first layer formed from a flexible film or sheet and a second layer formed with a conventional low-tack non-reactive reusable adhesive effective for attaching the substrate to drywall or plaster or wood surfaces. At least one rigid component is attached to the substrate. The second layer covers at least a portion of the first layer for attaching to a vertical surface and includes a release area, wherein the release area is positioned such that it is vertically above the at least one rigid component. The rigid component operates to produce a cantilever moment and wherein the release area operates to counteract the cantilever moment.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: March 3, 2020
    Assignee: ORIBEL PTE. LTD.
    Inventors: Su Min Goh, Liang Yi Chen
  • Publication number: 20190340328
    Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.
    Type: Application
    Filed: April 19, 2019
    Publication date: November 7, 2019
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20190280115
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
  • Patent number: 10326003
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
  • Patent number: 10297690
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao
  • Patent number: 10177663
    Abstract: A multi-phase power controller coupled to resonant power converting circuits providing an output voltage is disclosed. The multi-phase power controller includes a current sensing unit, a frequency adjusting circuit and a duty cycle adjusting circuit. The current sensing unit, coupled to a first resonant power converting circuit, provides a first sensing current. The frequency adjusting circuit includes an error amplifier and a first ramp signal generation circuit. The error amplifier provides an error signal according to the output voltage and a reference voltage. The first ramp signal generation circuit provides a first ramp signal according to the error signal. The duty cycle adjusting circuit provides a first PWM signal to the first resonant power converting circuit according to a default voltage and the first ramp signal. The change of the duty cycle of the first PWM signal is related to the first sensing current, the default voltage and the first ramp signal.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: January 8, 2019
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Hsien-Cheng Liu, Zhao-Wai Liu, Liang-Yi Chen
  • Patent number: 10158018
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Ming Lee, Liang-Yi Chen, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20180351459
    Abstract: A multi-phase power controller coupled to resonant power converting circuits providing an output voltage is disclosed. The multi-phase power controller includes a current sensing unit, a frequency adjusting circuit and a duty cycle adjusting circuit. The current sensing unit, coupled to a first resonant power converting circuit, provides a first sensing current. The frequency adjusting circuit includes an error amplifier and a first ramp signal generation circuit. The error amplifier provides an error signal according to the output voltage and a reference voltage. The first ramp signal generation circuit provides a first ramp signal according to the error signal. The duty cycle adjusting circuit provides a first PWM signal to the first resonant power converting circuit according to a default voltage and the first ramp signal. The change of the duty cycle of the first PWM signal is related to the first sensing current, the default voltage and the first ramp signal.
    Type: Application
    Filed: May 24, 2018
    Publication date: December 6, 2018
    Inventors: HSIEN-CHENG LIU, ZHAO-WAI LIU, LIANG-YI CHEN
  • Publication number: 20180192793
    Abstract: An article for mounting to a vertical surface comprising a substrate having a first layer formed from a flexible film or sheet and a second layer formed with a conventional low-tack non-reactive reusable adhesive effective for attaching the substrate to drywall or plaster or wood surfaces. At least one rigid component is attached to the substrate. The second layer covers at least a portion of the first layer for attaching to a vertical surface and includes a release area, wherein the release area is positioned such that it is vertically above the at least one rigid component. The rigid component operates to produce a cantilever moment and wherein the release area operates to counteract the cantilever moment.
    Type: Application
    Filed: July 15, 2016
    Publication date: July 12, 2018
    Applicant: ORIBEL PTE. LTD.
    Inventors: Su Min GOH, Liang Yi CHEN
  • Publication number: 20180190810
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Application
    Filed: October 4, 2017
    Publication date: July 5, 2018
    Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
  • Publication number: 20180033882
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 1, 2018
    Inventors: Hsueh-Chang SUNG, Liang-Yi CHEN
  • Publication number: 20170317205
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 2, 2017
    Inventors: Chen-Ming LEE, Liang-Yi CHEN, Fu-Kai YANG, Mei-Yun WANG
  • Patent number: 9793404
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Liang-Yi Chen
  • Patent number: 9685439
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Ming Lee, Liang-Yi Chen, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20170154990
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Hsueh-Chang Sung, Liang-Yi CHEN
  • Publication number: 20110100556
    Abstract: A plasma system with an injection device is provided. The plasma system comprises a plasma cavity and an injection device. The plasma cavity comprises a first electrode and a second for generating plasma. The injection device comprises a plasma injection tube and at least a reactant injection tube. The plasma injection tube is connected to the plasma cavity. The plasma injection tube comprises an inlet, an outlet and an outer sidewall. The plasma injection tube injects the plasma from the inlet and guides the plasma out through the outlet. The outer sidewall has a width decreasing from the inlet to the outlet. The reactant injection tube is disposed outside of the outer sidewall. The reactant injection tube injects a reactant to the outer sidewall so that the reactant flows along the outer sidewall toward the outlet and mixes with the plasma at the outlet.
    Type: Application
    Filed: December 24, 2009
    Publication date: May 5, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Hung Liu, Chen-Der Tsai, Wen-Tung Hsu, Chun-Hsien Su, Wen-Chin Cheng, Liang-Yi Chen
  • Patent number: 7854416
    Abstract: A display including a body and an elevation adjusting base is provided. The elevation adjusting base is secured to the body. The elevation adjusting base includes a base, an elevation adjusting mechanism, an outer bushing, an inner bushing and a friction ring. The elevation adjusting mechanism is connected to the base. The outer bushing is connected to the base and mounted on the elevation adjusting mechanism. The inner bushing is embedded inside the outer bushing. The friction ring is disposed between the outer bushing and the inner bushing. After the elevation of the elevation adjusting mechanism is adjusted, the friction ring provides a friction force between the outer bushing and the inner bushing to fix the elevation of the elevation adjusting mechanism. Users can accurately adjust the elevation of the display panel according to the view-angle and personal preferences.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: December 21, 2010
    Assignee: Qisda Corporation
    Inventors: Liang-Yi Chen, Chung-Hsien Chin
  • Patent number: 7391606
    Abstract: An electronic device comprises a body and an arm member disposed on the body. The body has a reference point. The arm member is moved between a first status, a second status and a third status. When the arm member is situated at the first status, the arm member relatively supports the body with respect to the reference point of the body. When the arm member is situated at the second status, the arm member relatively carries or suspends the body with respect to the reference point of the body.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: June 24, 2008
    Assignees: QISDA Corporation, BENQ Corporation
    Inventors: Liang-Yi Chen, Chung Hsien Chin