Patents by Inventor Liang-Yi Hung

Liang-Yi Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10174322
    Abstract: Disclosed herein is novel double-stranded short interfering ribonucleic acid (siRNA) capable of suppressing the translation of Aurora-A mRNA. Also disclosed are use of the novel siRNA as disclosed herein for manufacturing a medicament suitable for treating a cancer, which is mediated through epidermal growth factor receptor (EGFR) signaling. Accordingly, a pharmaceutical composition comprising the disclosed novel siRNA molecules is provided; as well as a method of treating a subject suffering from EGFR-mediated cancer via administering to the subject the disclosed novel siRNA molecule.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 8, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Liang-Yi Hung, Chien-Hsien Lai, Ta-Chien Tseng, Jeng-Chang Lee, Bo-Wen Lin
  • Patent number: 10096491
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 9, 2018
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Publication number: 20180037888
    Abstract: Disclosed herein is novel double-stranded short interfering ribonucleic acid (siRNA) capable of suppressing the translation of Aurora-A mRNA. Also disclosed are use of the novel siRNA as disclosed herein for manufacturing a medicament suitable for treating a cancer, which is mediated through epidermal growth factor receptor (EGFR) signaling. Accordingly, a pharmaceutical composition comprising the disclosed novel siRNA molecules is provided; as well as a method of treating a subject suffering from EGFR-mediated cancer via administering to the subject the disclosed novel siRNA molecule.
    Type: Application
    Filed: February 23, 2016
    Publication date: February 8, 2018
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Liang-Yi HUNG, Chien-Hsien LAI, Ta-Chien TSENG, Jeng-Chang LEE, Bo-Wen LIN
  • Patent number: 9607923
    Abstract: An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal conductor, wherein a width of the thermal conductor is smaller than a width of the electronic element. The thermal conductor includes silver to thereby greatly increase the thermal conductivity of the thermal conductor and hence improve the thermal conduction efficiency of the electronic device.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Jen Hung, Chi-An Pan, Chi-Hsiang Hsu, Liang-Yi Hung
  • Patent number: 9542598
    Abstract: A method for fabricating a package structure is provided, including the steps of: disposing and electrically connecting a sensing chip to a substrate; forming an encapsulant on the substrate to encapsulate the sensing chip; and forming a bright layer on the encapsulant to increase the gloss of the package structure. The encapsulant includes an additive to increase the Mohs hardness of the encapsulant. Further, the encapsulant with different additives presents different colors. Therefore, the invention obtains a high-gloss, high-hardness and colorful sensor package structure.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: January 10, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Yu Teng, Liang-Yi Hung
  • Publication number: 20160329261
    Abstract: An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal conductor, wherein a width of the thermal conductor is smaller than a width of the electronic element. The thermal conductor includes silver to thereby greatly increase the thermal conductivity of the thermal conductor and hence improve the thermal conduction efficiency of the electronic device.
    Type: Application
    Filed: December 24, 2015
    Publication date: November 10, 2016
    Inventors: Chung-Jen Hung, Chi-An Pan, Chi-Hsiang Hsu, Liang-Yi Hung
  • Publication number: 20160172264
    Abstract: A method for fabricating a package structure is provided, including the steps of: disposing and electrically connecting a sensing chip to a substrate; forming an encapsulant on the substrate to encapsulate the sensing chip; and forming a bright layer on the encapsulant to increase the gloss of the package structure. The encapsulant includes an additive to increase the Mohs hardness of the encapsulant. Further, the encapsulant with different additives presents different colors. Therefore, the invention obtains a high-gloss, high-hardness and colorful sensor package structure.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 16, 2016
    Inventors: Wen-Yu Teng, Liang-Yi Hung
  • Publication number: 20150303073
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Application
    Filed: June 30, 2015
    Publication date: October 22, 2015
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Patent number: 9112063
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20150179598
    Abstract: A flip-chip packaging structure is provided, which includes: a packaging substrate having a substrate body and a circuit layer formed on the substrate body, wherein the circuit layer has a plurality of conductive pads embedded in the substrate body and exposed from a surface of the substrate body; and a chip disposed on and electrically connected to the packaging substrate through a plurality of conductive elements, wherein the conductive elements and the exposed portions of the conductive pads have a width ratio in a range of 0.7 to 1.3, thereby improving the product yield and reliability.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 25, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Shih-Chao Chiu, Liang-yi Hung
  • Publication number: 20150102484
    Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 16, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Liang-yi Hung, Wei-chung Hsiao, Yu-cheng Pai, Shih-Chao Chiu, Don-Son Jiang, Yi-Feng Chang, Lung-Yuan Wang
  • Publication number: 20150028485
    Abstract: A substrate structure is provided. The substrate structure includes a substrate body; a metal layer formed on a surface of the substrate body; an insulating layer formed on the surface of the substrate body and having at least an opening for exposing the metal layer; and at least a die attach area defined on the surface of the substrate body corresponding in position to the opening for a semiconductor chip to be disposed thereon. The die attach area covers the entire opening or the metal layer is formed within the die attach area, thereby effectively preventing package delamination and improving the product yield.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Liang-Yi Hung, Shih-Chao Chih, Yu-Cheng Pai, Wei-Chung Hsiao
  • Publication number: 20140308780
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Patent number: 8796867
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: August 5, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20140057410
    Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.
    Type: Application
    Filed: November 20, 2012
    Publication date: February 27, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Wei-Chung Hsiao, Ming-Chen Sun, Liang-Yi Hung
  • Publication number: 20130307152
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Application
    Filed: August 17, 2012
    Publication date: November 21, 2013
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20130228921
    Abstract: A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 5, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Liang-Yi Hung, Yu-Cheng Pai, Wei-Chung Hsiao, Chun-Hsien Lin, Ming-Chen Sun
  • Patent number: 8471383
    Abstract: A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 25, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Liang-Yi Hung, Yu Cheng Pai, Ming Chen Sun, Chun Hsien Lin
  • Publication number: 20130026657
    Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 31, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Chung Hsiao, Chun- Hsien Lin, Yu-Cheng Pai, Liang-Yi Hung, Ming-Chen Sun
  • Publication number: 20120326305
    Abstract: A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.
    Type: Application
    Filed: September 23, 2011
    Publication date: December 27, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Liang-Yi Hung, Yu Cheng Pai, Ming Chen Sun, Chun Hsien Lin