Patents by Inventor Liang-Yi Hung

Liang-Yi Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130307152
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Application
    Filed: August 17, 2012
    Publication date: November 21, 2013
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20130228921
    Abstract: A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 5, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Liang-Yi Hung, Yu-Cheng Pai, Wei-Chung Hsiao, Chun-Hsien Lin, Ming-Chen Sun
  • Patent number: 8471383
    Abstract: A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 25, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Liang-Yi Hung, Yu Cheng Pai, Ming Chen Sun, Chun Hsien Lin
  • Publication number: 20130026657
    Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 31, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Chung Hsiao, Chun- Hsien Lin, Yu-Cheng Pai, Liang-Yi Hung, Ming-Chen Sun
  • Publication number: 20120326305
    Abstract: A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.
    Type: Application
    Filed: September 23, 2011
    Publication date: December 27, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Liang-Yi Hung, Yu Cheng Pai, Ming Chen Sun, Chun Hsien Lin
  • Patent number: 7449563
    Abstract: Polypeptides that comprise an approximately 100-amino acid residue region of a centrosomal P4.1-associated protein (CPAP) that possess microtubule-destabilizing activity, polynucleotides encoding such polypeptides, compositions comprising the polypeptides and polynucleotides, and methods of use thereof, are disclosed. The invention is useful for destabilizing microtubules in eukaryotic cells, including but not limited to cancer cells.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 11, 2008
    Assignee: Academia Sinica
    Inventors: Tang K. Tang, Liang-Yi Hung, Ching-Wen Chang
  • Publication number: 20080164604
    Abstract: A heat dissipating semiconductor package is disclosed, including a chip carrier; at least a semiconductor chip mounted and electrically connected to the chip carrier; and a heat dissipating member mounted on the semiconductor chip with a thermal interface material (TIM) interposed therebetween, wherein the TIM is provided with a plurality of fillers for supporting the TIM at an appropriate height, thereby preventing the TIM from being wetted so as to avoid collapsing and overflow of the TIM as a result of wetting problem.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Liang-Yi Hung, Yu-Po Wang, Cheng-Hsu Hsiao
  • Publication number: 20080150128
    Abstract: A heat dissipating chip structure and a fabrication method thereof and a package having the same are provided. The fabrication method mainly includes: forming a metal layer on an non-active surface of a wafer having a plurality of chips with the metal layer thereof providing a better solder bonding with a thermal interface material at positions corresponding to centers of each chips, and not being disposed on the cutting paths between the chips to prevent crack and peel off during the cutting. Further, when the chips are subsequently mounted on a chip carrier and further attached to a heat dissipating sheet with another metal layer on a surface thereof with the thermal interface material (TIM), with different surface areas of the metal layers formed on the heat dissipating sheet and the chip, an inward and downward force is generated in the TIM to limit an wetting area.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 26, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Liang-Yi Hung, Yu-Po Wang, Cheng-Hsu Hsiao
  • Publication number: 20050089921
    Abstract: Polypeptides that comprise an approximately 100-amino acid residue region of a centrosomal P4.1-associated protein (CPAP) that possess microtubule-destabilizing activity, polynucleotides encoding such polypeptides, compositions comprising the polypeptides and polynucleotides, and methods of use thereof, are disclosed. The invention is useful for destabilizing microtubules in eukaryotic cells, including but not limited to cancer cells.
    Type: Application
    Filed: December 3, 2004
    Publication date: April 28, 2005
    Applicant: Academia Sinica
    Inventors: Tang Tang, Liang-Yi Hung, Ching-Wen Chang
  • Patent number: 6864238
    Abstract: Polypeptides that comprise an approximately 100-amino acid residue region of a centrosomal P4.1-associated protein (CPAP) that possess microtubule-destabilizing activity, polynucleotides encoding such polypeptides, compositions comprising the polypeptides and polynucleotides, and methods of use thereof, are disclosed. The invention is useful for destabilizing microtubules in eukaryotic cells, including but not limited to cancer cells.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: March 8, 2005
    Assignee: Academia Sinica
    Inventors: Tang K. Tang, Liang-Yi Hung, Ching-Wen Chang