Patents by Inventor Liang Yin
Liang Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12389662Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.Type: GrantFiled: May 17, 2022Date of Patent: August 12, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Szu-Ying Chen, Chia-Cheng Chen, Liang-Yin Chen, Sen-Hong Syue
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Publication number: 20250254939Abstract: A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.Type: ApplicationFiled: April 25, 2025Publication date: August 7, 2025Inventors: Chun-Hung Wu, Chia-Ling Chung, Su-Hao Liu, Liang-Yin Chen, Shun-Wu Lin, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12374519Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.Type: GrantFiled: August 27, 2021Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chun-Liang Chen, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250241029Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.Type: ApplicationFiled: April 11, 2025Publication date: July 24, 2025Inventors: Yu-Chang Lin, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250232985Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.Type: ApplicationFiled: April 7, 2025Publication date: July 17, 2025Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12354873Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.Type: GrantFiled: June 21, 2021Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Kai Yang, Yu-Tien Shen, Hsiang-Ming Chang, Chun-Yen Chang, Ya-Hui Chang, Wei-Ting Chien, Chia-Cheng Chen, Liang-Yin Chen
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Patent number: 12347681Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.Type: GrantFiled: July 31, 2023Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
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Publication number: 20250210414Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.Type: ApplicationFiled: March 12, 2025Publication date: June 26, 2025Inventors: Kuo-Ju Chen, Shih-Hsiang Chiu, Meng-Han Chou, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12331287Abstract: The present invention generally relates to droplets and/or emulsions, such as multiple emulsions. In some cases, the droplets and/or emulsions may be used in assays, and in certain embodiments, the droplet or emulsion may be hardened to form a gel. For example, a droplet may be hardened to form a gel, where the droplet contains a cell, DNA, or other suitable species. The gel may be exposed to a reactant, and the reactant may interact with the gel and/or with the cell, DNA, etc., in some fashion. For example, the reactant may diffuse through the gel, or the hardened particle may liquefy to form a liquid state, allowing the reactant to interact with the cell. As the DNA is amplified using PCR, some of the DNA will be bound to the gel via the PCR primer.Type: GrantFiled: November 26, 2024Date of Patent: June 17, 2025Assignee: President and Fellows of Harvard CollegeInventors: David A. Weitz, Jeremy Agresti, Liang-Yin Chu, Jin-Woong Kim, Amy Rowat, Morten Sommer, Gautam Dantas, George M. Church
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Patent number: 12322916Abstract: The disclosure relates to an apparatus for connecting an electronic component to a conductor. A housing includes at least one slot and defines at least one component chamber for carrying the electronic component. A liquid coolant can pass through the housing. A pair of conductive members extends from the housing through the at least one slot and can be releasably inserted into a channel defined in a support assembly. The support assembly facilitates an electrical connection between the conductive members and corresponding conductive contact members connected to a respective power supply or electrical load. The support assembly can provide an inward sealing force to a seal on the housing circumscribing the pair of conductive members.Type: GrantFiled: June 22, 2022Date of Patent: June 3, 2025Assignee: GE AVIATION SYSTEMS LLCInventors: Christopher James Kapusta, David Richard Esler, Arun Virupaksha Gowda, Brian Magann Rush, Liang Yin, Richard Anthony Eddins, Liqiang Yang, Judd Everett Swanson
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Patent number: 12317551Abstract: A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.Type: GrantFiled: December 30, 2021Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Wu, Chia-Ling Chung, Su-Hao Liu, Liang-Yin Chen, Shun-Wu Lin, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12314175Abstract: Various embodiments include techniques for managing cache memory in a computing system. The computing system includes a sectored cache memory that provides a mechanism for software applications to directly invalidate data items stored in the cache memory on a sector-by-sector basis, where a sector is smaller than a cache line. When all sectors in a cache line have been invalidated, the cache line is implicitly invalidated, freeing the cache line to be reallocated for other purposes. In cases where the data items to be invalidated can be aligned to sector boundaries, the disclosed techniques effectively use status indicators in the cache tag memory to track which sectors, and corresponding data items, have been invalidated by the software application. Thus, the disclosed techniques thereby enable a low-overhead solution for invalidating individual data items that are smaller than a cache line without additional tracking data structures or consuming additional memory transfer bandwidth.Type: GrantFiled: March 23, 2022Date of Patent: May 27, 2025Assignee: NVIDIA CORPORATIONInventors: Michael Fetterman, Shirish Gadre, Steven James Heinrich, Martin Stich, Liang Yin
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Patent number: 12315753Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.Type: GrantFiled: November 28, 2023Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12317524Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.Type: GrantFiled: July 28, 2022Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
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Publication number: 20250169132Abstract: A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species in the amorphous region, and performing a second implantation process to implant a second species in the amorphous region. The second species includes fluorine, nitrogen, or carbon. The method further includes performing an annealing process to recrystallize the amorphous region.Type: ApplicationFiled: January 30, 2024Publication date: May 22, 2025Inventors: Yu-Chang LIN, Sih-Jie LIU, Chun-Hung WU, Liang-Yin CHEN, Chi On CHUI
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Publication number: 20250155759Abstract: A transparent display apparatus includes a first transparent substrate, first signal lines, second signal lines, pixel structures, transparent insulation patterns, a second transparent substrate and an electrochromic material. The first transparent substrate has a circuit area, pixel areas and light modulation areas. The first signal lines and the second signal lines cross with each other and are arranged in the circuit area. The pixel structures are respectively arranged in the pixel areas and are electrically connected to the first signal lines and the second signal lines. Each of the light modulation areas is surrounded by a part of the pixel structures. The transparent insulation patterns are disposed on the first transparent substrate and cover the pixel structures respectively. The second transparent substrate is disposed opposite to the first transparent substrate.Type: ApplicationFiled: October 10, 2024Publication date: May 15, 2025Applicant: AUO CorporationInventors: Liang-Yin Huang, Kun-Cheng Tien
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Patent number: 12300717Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.Type: GrantFiled: February 14, 2022Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chang Lin, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 12293924Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.Type: GrantFiled: January 17, 2024Date of Patent: May 6, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20250126874Abstract: A method includes a number of operations. An interlayer dielectric (ILD) layer is formed over a source/drain region on a substrate. A source/drain contact extending through the ILD layer to electrically connect with the source/drain region is formed. An air gap extending through the ILD layer is formed. An implantation energy absorption dielectric layer is formed over the ILD layer. An implantation process is performed on the implantation energy absorption dielectric layer, wherein the implantation process causes the ILD layer expands to seal the air gap. A first implant-free dielectric layer is formed over the implantation energy absorption dielectric layer. A second implant-free dielectric layer is formed over the first implant-free dielectric layer. A source/drain via extending through the second implant-free dielectric layer, the first implant-free dielectric layer, and the implantation energy absorption dielectric layer to the source/drain contact is formed.Type: ApplicationFiled: October 16, 2023Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ju CHEN, Te-Jui YEN, Liang-Yin CHEN, Chi On CHUI
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Publication number: 20250126859Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.Type: ApplicationFiled: October 12, 2023Publication date: April 17, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang LIN, Sih-Jie LIU, Po-Kang HO, Liang-Yin CHEN, Tsai-Yu HUANG, Chi On CHUI