Patents by Inventor Liang-Yi Chen
Liang-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106246Abstract: Disclosed is a power storage device and method for discharging the same, which configures the power storage device to perform an electric power output under a discharging limit upon coupling with a load device and before any authentication is conducted. The discharging limit for the electric power output will be lifted only when an authentication result between the power storage device and the load device indicates a successful authentication.Type: ApplicationFiled: September 27, 2023Publication date: March 28, 2024Inventors: Wei-Tsung Huang, I-Sheng Chen, Liang-Yi Hsu
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Patent number: 11907636Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: GrantFiled: July 8, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, Kuopei Lu, Lester Chang, Ze-Ming Wu
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Publication number: 20230268390Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai CHENG, Liang-Yi CHEN, Chi-An WANG, Kuan-Chung CHEN, Chih-Wei LEE
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Publication number: 20220343054Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20220238709Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
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Patent number: 11392749Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: GrantFiled: November 18, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 11309418Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: GrantFiled: May 20, 2019Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao
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Patent number: 11145759Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.Type: GrantFiled: October 12, 2017Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang Sung, Liang-Yi Chen
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Publication number: 20210073454Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Patent number: 10846456Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: GrantFiled: April 19, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 10575664Abstract: An article for mounting to a vertical surface comprising a substrate having a first layer formed from a flexible film or sheet and a second layer formed with a conventional low-tack non-reactive reusable adhesive effective for attaching the substrate to drywall or plaster or wood surfaces. At least one rigid component is attached to the substrate. The second layer covers at least a portion of the first layer for attaching to a vertical surface and includes a release area, wherein the release area is positioned such that it is vertically above the at least one rigid component. The rigid component operates to produce a cantilever moment and wherein the release area operates to counteract the cantilever moment.Type: GrantFiled: July 15, 2016Date of Patent: March 3, 2020Assignee: ORIBEL PTE. LTD.Inventors: Su Min Goh, Liang Yi Chen
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Publication number: 20190340328Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: ApplicationFiled: April 19, 2019Publication date: November 7, 2019Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20190280115Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: ApplicationFiled: May 20, 2019Publication date: September 12, 2019Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
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Patent number: 10297690Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: GrantFiled: October 4, 2017Date of Patent: May 21, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao
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Patent number: 10177663Abstract: A multi-phase power controller coupled to resonant power converting circuits providing an output voltage is disclosed. The multi-phase power controller includes a current sensing unit, a frequency adjusting circuit and a duty cycle adjusting circuit. The current sensing unit, coupled to a first resonant power converting circuit, provides a first sensing current. The frequency adjusting circuit includes an error amplifier and a first ramp signal generation circuit. The error amplifier provides an error signal according to the output voltage and a reference voltage. The first ramp signal generation circuit provides a first ramp signal according to the error signal. The duty cycle adjusting circuit provides a first PWM signal to the first resonant power converting circuit according to a default voltage and the first ramp signal. The change of the duty cycle of the first PWM signal is related to the first sensing current, the default voltage and the first ramp signal.Type: GrantFiled: May 24, 2018Date of Patent: January 8, 2019Assignee: UPI SEMICONDUCTOR CORP.Inventors: Hsien-Cheng Liu, Zhao-Wai Liu, Liang-Yi Chen
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Patent number: 10158018Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.Type: GrantFiled: May 9, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ming Lee, Liang-Yi Chen, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20180351459Abstract: A multi-phase power controller coupled to resonant power converting circuits providing an output voltage is disclosed. The multi-phase power controller includes a current sensing unit, a frequency adjusting circuit and a duty cycle adjusting circuit. The current sensing unit, coupled to a first resonant power converting circuit, provides a first sensing current. The frequency adjusting circuit includes an error amplifier and a first ramp signal generation circuit. The error amplifier provides an error signal according to the output voltage and a reference voltage. The first ramp signal generation circuit provides a first ramp signal according to the error signal. The duty cycle adjusting circuit provides a first PWM signal to the first resonant power converting circuit according to a default voltage and the first ramp signal. The change of the duty cycle of the first PWM signal is related to the first sensing current, the default voltage and the first ramp signal.Type: ApplicationFiled: May 24, 2018Publication date: December 6, 2018Inventors: HSIEN-CHENG LIU, ZHAO-WAI LIU, LIANG-YI CHEN
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Publication number: 20180192793Abstract: An article for mounting to a vertical surface comprising a substrate having a first layer formed from a flexible film or sheet and a second layer formed with a conventional low-tack non-reactive reusable adhesive effective for attaching the substrate to drywall or plaster or wood surfaces. At least one rigid component is attached to the substrate. The second layer covers at least a portion of the first layer for attaching to a vertical surface and includes a release area, wherein the release area is positioned such that it is vertically above the at least one rigid component. The rigid component operates to produce a cantilever moment and wherein the release area operates to counteract the cantilever moment.Type: ApplicationFiled: July 15, 2016Publication date: July 12, 2018Applicant: ORIBEL PTE. LTD.Inventors: Su Min GOH, Liang Yi CHEN
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Publication number: 20180190810Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.Type: ApplicationFiled: October 4, 2017Publication date: July 5, 2018Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
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Publication number: 20180033882Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.Type: ApplicationFiled: October 12, 2017Publication date: February 1, 2018Inventors: Hsueh-Chang SUNG, Liang-Yi CHEN