Abstract: A display substrate and a display device. The display substrate includes a base substrate, a plurality of cathode lines, a planarization layer, a pixel definition layer, and a plurality of light emitting elements; the plurality of cathode lines are located on the base substrate; the planarization layer is located at a side of the cathode lines away from the base substrate; the pixel definition layer is located at a side of the planarization layer away from the cathode lines; the display substrate further includes a plurality of conductive isolation columns, the conductive isolation columns are arranged in one-to-one correspondence with the light emitting elements, each conductive isolation column is electrically connected with one cathode line, and each light emitting element includes an anode, a light emitting layer and a cathode, and the cathode of each light emitting element is electrically connected with a corresponding conductive isolation column.

Abstract: A display substrate includes: a base substrate; a plurality of first barrier structures arranged in an array on a side of the base substrate, each of the first barrier structures enclosing a first region; and a first electrode layer comprising a plurality of first electrodes, the plurality of first electrodes being arranged corresponding to the plurality of first barrier structures, and each of the first electrodes being within the first region enclosed by the corresponding first barrier structure, wherein each of the first barrier structures has a first height in a thickness direction of the base substrate, each of the first electrodes has a second height in the thickness direction of the base substrate, the first height is greater than the second height, and a separation groove is provided on a side surface of each of the first barrier structures away from the base substrate.

Abstract: A shift register unit, a gate drive circuit, a display panel, and a driving method. An example shift register unit includes: a first shift register, which is configured to output a cascade signal by a cascade output end; a sampling circuit, which is coupled to a first node and is configured to provide a signal at an enabling end to the first node in response to a signal at a sampling control end; and a control circuit, which is coupled to the cascade output end and the first node, and is configured to output, in response to a signal of the first node, a gate scanning signal having the same time sequence as the cascade signal by a driving output end, or to output a gate cut-off signal by the driving output end.

Abstract: A gate driving unit includes a charge pump circuit and an output circuit; the charge pump circuit is connected to a first input node, an input clock signal terminal and a first node; the charge pump circuit is configured to control a voltage signal of the first input node under the control of an input clock signal provided by the input clock signal terminal, the voltage signal of the first input node is written into the first node when the voltage signal of the first input node is a first voltage signal; the output circuit comprises a first output transistor, a control electrode of the first output transistor is connected to the first node, a first electrode of the first output transistor is connected to an output voltage terminal, and a second electrode of the first output transistor is connected to a gate driving signal output terminal.

Abstract: A display substrate and a display device. The display substrate includes: a base substrate; and a gate driving circuit; the gate driving circuit includes a plurality of shift register circuits; each shift register circuit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit; the control circuit includes a first transistor, a second transistor, and a third transistor; the control circuit is connected to the first node, a second node and a third node; at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor extend in a first direction and are arranged in the first direction.

Abstract: Provided are a high-strength and high-impact toughness near-? titanium alloy, and a preparation method and use thereof, belonging to the technical field of titanium alloy. The high-strength and high-impact toughness near-? titanium alloy provided includes chemical elements as follows: in percentage by mass, 3.2-4.5% of Mo, 2.5-4% of Cr, 0.5-1.8% of Fe, and 0.5-3% of Al, with a balance being Ti and unavoidable impurities, a component ratio of which satisfies 9<[Mo]eq<11; where the high-strength and high-impact toughness near-? titanium alloy has a metallographic structure including a coarse ?-lamellar structure and a fine ?-lamellar structure.

Abstract: A display substrate is provided. In the display substrate, adjacent ones of the plurality of first groups are staggered so that a line connecting centers of four sub-pixels including two second sub-pixels and two third sub-pixels that are in the adjacent ones of the plurality of first groups and are adjacent to one another constitute a first trapezoid, a first straight line in the second direction passes through one of the two second sub-pixels and one of the two third sub-pixels that are located on a waist of the first trapezoid, and has two intersection points with the one of the two second sub-pixels and the one of the two third sub-pixels, respectively.

Abstract: A display substrate includes: a first display region (A1). The first display region (A1) includes multiple display island regions (A11) spaced apart from each other, a light-transmissive region (A12) between adjacent display island regions, and a connection region (A13) connecting adjacent display island regions (A11). A display island region (A11) includes a first pixel unit (P1). The first pixel unit (P1) includes: a first region pixel circuit (13) and a first region light-emitting element (11). The display island region (A11) has an arc edge.

Abstract: Disclosed are a shift register unit, a gate drive circuit, a display device, and a driving method thereof. The shift register unit includes an input circuit, a node control circuit, a first control output circuit, a second control output circuit and an output circuit. The output circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a first electrode of the eleventh transistor is coupled to the input circuit, and a second electrode of the eleventh transistor is coupled to a gate electrode of the thirteenth transistor; a first electrode of the twelfth transistor is coupled to the first electrode of the eleventh transistor; the eleventh transistor and the twelfth transistor are configured to provide a signal the gate electrode of the thirteenth transistor.

Abstract: A pixel driving circuit, a driving method for the pixel driving circuit and a display panel are provided. The pixel driving circuit includes: a driving transistor, a first reset sub-circuit, a second reset sub-circuit, a luminescent control sub-circuit, a data writing sub-circuit, a gating sub-circuit and an energy storage element. The first reset sub-circuit is configured to write a first initialization voltage signal to a control electrode of the driving transistor in response to a first reset signal; the second reset sub-circuit is configured to write a second initialization voltage signal to a first electrode of at least one light-emitting device in response to a second reset signal; the luminescent control sub-circuit is configured to electrically connect a first power supply line to the first electrode of the driving transistor in response to one of a first luminescent control signal and a second luminescent control signal.

Abstract: A display substrate and a display device are provided. In the display substrate, the shift register unit includes a charge pump circuit, the charge pump circuit includes a first capacitor and a first transistor, the charge pump circuit is electrically connected with a first input node and a first node, respectively; a first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a gate electrode of the first transistor is connected with a first electrode of the first transistor, the second electrode plate of the first capacitor is provided with a first portion, the first portion of the second electrode plate of the first capacitor and the gate electrode of the first transistor have an integral structure, an active layer of the first transistor extends in a second direction.

Abstract: A display panel includes a base substrate, a first metal layer, and a second metal layer. The first metal layer is located on a side of the base substrate. The first metal layer includes a plurality of fan-out transposition lines. The second metal layer is located on a side of the first metal layer facing away from the base substrate. The second metal layer includes a plurality of data signal lines and a plurality of data fan-out lines. At least some of the data signal lines distant from a middle area of the display panel are connected to the fan-out transposition lines by means of via holes, and the fan-out transposition lines are further connected to the data fan-out lines proximate to the middle area of the display panel by means of via holes.

Abstract: A display panel and a display device are provided. The display panel includes a pixel driving circuit on a side of a substrate. The pixel driving circuit includes a drivier transistor; a ninth transistor with a first electrode being connected to a third initial signal line, and a second electrode being connected to a first electrode of the driver transistor; an eighth transistor with a first electrode being connected to a gate of the driver transistor; a first transistor with a first electrode being connected to a first initial signal line, and a second electrode being connected to a second electrode of the eighth transistor; and a second transistor with a first electrode being connected to the second electrode of the eighth transistor, and a second electrode being connected to a second electrode of the driver transistor.

Abstract: An array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit includes a driving transistor, a data write transistor, a first capacitor including a first capacitor electrode and a second capacitor electrode, and a second capacitor including a third capacitor electrode and a fourth capacitor electrode. The second capacitor electrode and the third capacitor electrode are coupled to a second electrode of the data write transistor. The array substrate includes a stacked structure of capacitor electrodes. The stacked structure includes the first capacitor electrode; an insulating layer on the first capacitor electrode; an electrode block including the second capacitor electrode and the third capacitor electrode on a side of the insulating layer away from the first capacitor electrode; an inter-layer dielectric layer on a side of the electrode block away from the insulating layer; and the fourth capacitor electrode on the inter-layer dielectric layer.

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first control circuit, a compensation control circuit and a first initialization circuit; the first control circuit is configured to control to connect the control end of the driving circuit and the connection node under the control of a first scan signal; the compensation control circuit is configured to control to connect the connection node and the first end of the driving circuit under the control of a second scan signal; the first initialization circuit is configured to write a first initialization voltage into the connection node under the control of an initialization control signal; the driving circuit is configured to control to connect the first end and a second end of the driving circuit under the control of a potential of the control end thereof.

Abstract: A gate driving unit includes a charge pump circuit and an output circuit; the charge pump circuit is connected to a first input node, an input clock signal terminal and a first node; the charge pump circuit is configured to control a voltage signal of the first input node under the control of an input clock signal provided by the input clock signal terminal, the voltage signal of the first input node is written into the first node when the voltage signal of the first input node is a first voltage signal; the output circuit comprises a first output transistor, a control electrode of the first output transistor is connected to the first node, a first electrode of the first output transistor is connected to an output voltage terminal, and a second electrode of the first output transistor is connected to a gate driving signal output terminal.

Abstract: A display panel and a display apparatus are provided.

Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a driving circuit, a first initialization circuit and a reset circuit; the first initialization circuit configured to write a first initial voltage into the first end of the driving circuit under the control of an initialization control signal; the reset circuit is configured to write a reset voltage into the second end of the driving circuit or the first end of the driving circuit under the control of a second scan signal; the driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of a control end of the driving circuit.

Abstract: A pixel circuit includes a pixel driving circuit, a first light-emitting element, a second light-emitting element, a switching circuit including a first terminal, a second terminal and a control terminal, and a reset circuit. The pixel driving circuit is electrically connected to the first light-emitting element the first terminal is electrically connected to the pixel driving circuit, the second terminal is electrically connected to the second light-emitting element, the switching circuit is configured to: electrically connect the second light-emitting element to the pixel driving circuit in response to the control terminal receiving a first level signal, and disconnect an electrical connection between the second light-emitting element and the pixel driving circuit in response to the control terminal receiving a second level signal.

Abstract: A display substrate and a display device. The display substrate includes: a base substrate; and a gate driving circuit; the gate driving circuit includes a plurality of shift register circuits; each shift register circuit includes: an input circuit, a control circuit, an output circuit, and an output noise reduction circuit; the control circuit includes a first transistor, a second transistor, and a third transistor; the control circuit is connected to the first node, a second node and a third node; at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor extend in a first direction and are arranged in the first direction.