Abstract: Provided is an organic light-emitting diode display substrate, including: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein the source/drain layer includes at least one pair of first signal lines; the anode layer includes a common power line, wherein the common power line is provided with vent holes; overlapping areas between two first signal lines in each pair of the first signal lines and a projection pattern of the vent hole are equal, the overlapping area being greater than 0, wherein the projection pattern of the vent hole is a pattern of an orthographic projection of the vent hole in the common power line on the source/drain layer. A display panel and a display device are also provided.

Abstract: Embodiments of the present disclosure disclose a shift register unit, a driving method thereof, and a device. The shift register unit includes an input circuit, a node control circuit, a first control output circuit, a second control output circuit and an output circuit. By providing the first control output circuit and the second control output circuit, the first control output circuit and the second control output circuit may operate alternately, so that the first control output circuit and the second control output circuit may have time for characteristics recovery respectively, thus improving the service life and output stability of the shift register unit.

Abstract: A display substrate includes a pixel driving circuit, which includes a driving circuit, a storage circuit and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit. The driving circuit is used to conduct a path between the first terminal and a second terminal of the driving circuit under the control of a potential at its control terminal. The storage circuit is electrically connected to the control terminal of the driving circuit. The reset circuit includes a first capacitor. The storage circuit includes a second capacitor. An area of an overlap between orthographic projections of a first electrode plate and a second electrode plate of the first capacitor on the base substrate is smaller than that of the second capacitor on the base substrate.

Abstract: Disclosed are a device and method for detecting defects of a high-voltage cable cross-bonded grounding system. The method comprises: selecting a protective grounding box of a cross-bonded grounding system, respectively connecting a signal excitation coupler to A-phase, B-phase and C-phase coaxial cables of the protective grounding box, selecting a stable signal with a frequency different from a power frequency or a field interference frequency, and testing effective current values and phases responded by the A-phase, B-phase and C-phase coaxial cables when the stable signal with the frequency F1 is injected into the A-phase, B-phase and C-phase coaxial cables of the protective grounding box in a coupled manner; and obtaining resistances and inductances of branch circuits of the cable cross-bonded grounding system by calculation according to measurement data, and determining if the cable cross-bonded grounding system has a connection defect.

Abstract: The present disclosure provides a display panel, a method of manufacturing the same, and a display device. The initialization signal line layer in the display panel includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas; the first auxiliary signal line layer includes a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area, at least part of the first auxiliary signal line pattern extends along the first direction, and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled.

Abstract: A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.

Abstract: A method for detecting abnormal direct current voltage measurement in a modular multilevel converter high voltage direct current transmission system is provided. In the method, a valve group voltage at a detection pole is obtained, voltages at voltage measurement points at the detection pole are collected, and comparison and determination are performed based on the actual arrangement of the voltage measurement points, and then whether an abnormal measurement occurs at each of the voltage measurement points is determined.

Abstract: Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof. The array substrate includes a substrate and a plurality of sub-pixels on the substrate. Each sub-pixel includes a pixel circuit. The pixel circuit includes a plurality of transistors. The plurality of transistors includes at least one oxide transistor. The array substrate further includes: an oxide semiconductor layer on the substrate, the oxide semiconductor layer comprising a channel region of the oxide transistor; a first planarization layer on the substrate and covering at least a portion of the oxide semiconductor layer; a barrier part on the side of the first planarization layer away from the substrate.

Abstract: A display substrate and a display device are provided, the display substrate includes: a substrate, and a power source layer, a conductive layer, and a cathode layer sequentially stacked on the substrate in a direction away from the substrate; the conductive layer includes first conductive patterns and second conductive patterns insulated from each other, the first conductive patterns are coupled to the power source layer, and the second conductive patterns are coupled to the cathode layer.

Abstract: A pixel circuit and a driving method therefor, an array substrate and a display device are provided. The pixel circuit includes a driving circuit, a data writing circuit, a first initialization circuit. The driving circuit is configured to control a driving current; the data writing circuit is configured to write a data signal into the control terminal of the driving circuit; the first initialization circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit, and includes a first transistor; the data writing circuit includes a second transistor and the driving circuit includes a third transistor; semiconductor materials of active layers of both the first transistor and the second transistor have a smaller leakage current characteristic than a semiconductor material of a third active layer of the third transistor.

Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels. The array substrate includes: a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction. Projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the projections of the power lines and the power leads on the base substrate form a grid-like structure.

Abstract: The disclosure relates to the technical field of alloys, and in particular to a titanium alloy with a gradient microstructure and a preparation method thereof. Two new gradient microstructures different from the existing microstructure in titanium alloy are designed for the first time by an ingenious three-step heat treatment scheme, specifically, the gradient lamellar microstructure and gradient tri-modal microstructure. Compared with the regular uniform lamellar microstructure, the titanium alloy with gradient lamellar microstructure can achieve the simultaneous improvement of strength and ductility. Compared with the regular bimodal microstructure, the strength of a titanium alloy with a gradient tri-modal microstructure can be increased by about 10%, and the ductility is slightly reduced.

Abstract: A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.

Abstract: Aspects are provided which allow a UE to achieve sidelink parameter coordination through various signaling in clustered FL or peer-to-peer FL. The UE provides a first ML model information update and a measurement associated with the update. The UE obtains an aggregated ML model information update aggregating the first update with a second ML model information update of either a first network node in a FL cluster including the UE or a second network node in a second FL cluster. The UE provides a sidelink communication parameter in SCI to a network node, which parameter is an output of an ML model associated with the aggregated ML model information update. As a result, UEs may derive common SCI parameters from their updated ML models to apply in sidelink communications, thereby leading to maximized packet reception rate, maximized throughput, or minimized latency in communication.

Abstract: A display substrate, a preparation method thereof, a display panel, and a display device are provided. The display substrate includes a base substrate and a repeating unit, the repeating unit includes a plurality of sub-pixels including a first sub-pixel and a second sub-pixel, a color of light emitted by a light-emitting element of the first sub-pixel is identical to a color of light emitted by a light-emitting element of the second sub-pixel, a shape of a first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel is different from a shape of a first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel.

Abstract: The present disclosure provides a display panel, a pixel circuit and a method for driving the pixel circuit, the pixel circuit includes: a storage capacitor circuit; a light-emitting element; a driving transistor; a reset circuit, the reset circuit is configured to receive a reset control signal and reset a first node and a second node according to the reset control signal, or receive a writing control signal and/or a timing sequence control signal of an adjacent pixel row and reset the first node and the second node according to the writing control signal and/or the timing sequence control signal of the adjacent pixel row; a threshold compensation circuit, configured to receive a compensation control signal and write a compensation voltage into the first node according to the compensation control signal; a writing circuit; and a light-emitting control circuit.

Abstract: A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.

Abstract: There is provided a display substrate, in which, a first reference voltage line and a first reference voltage auxiliary line, which extend in different directions, are respectively disposed in one of a second wiring layer, a third wiring layer and a fourth wiring layer, a second reference voltage line extends in the same direction as the first reference voltage auxiliary line, the first reference voltage auxiliary line is electrically coupled to the first reference voltage line through via holes in an insulating layer therebetween, via a coupling line extending in the same direction as the first reference voltage line, the first reference voltage auxiliary line and the first reference voltage line provide a reset voltage to a first electrode of a first capacitor, and the second reference voltage line provides a reset voltage to a pixel electrode in a pixel electrode layer. A display device is further provided.

Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: a second noise reduction control circuit. The second noise reduction control circuit includes: a first control circuit, configured to transmit a first voltage to a second noise reduction control node; a first coupling circuit, configured to store a level of the second noise reduction control node and adjust the level of the second noise reduction control node; a second coupling circuit, configured to reduce an adjustment magnitude of the first coupling circuit in case of adjusting the level of the second noise reduction control node; a transmission circuit, configured to connect the first noise reduction control node and the second noise reduction control node; and a storage circuit, configured to store the level of the first noise reduction control node.