Abstract: A display panel includes an array substrate and an encapsulation layer encapsulated on a surface of the array substrate. The display panel further includes a stretching area located in a corner area of the display panel and at least partially located in a display area of the display panel, and the stretching area is provided with a hollow opening penetrating through the array substrate and the encapsulation layer.

Abstract: The present disclosure provides a pixel circuit, a pixel driving method and a display device. The pixel circuit includes a driving circuit, an energy storage circuit and a switch control circuit. A first end of the energy storage circuit is coupled to a control end of the driving circuit, a second end of the energy storage circuit is coupled to a first end of the driving circuit via the switch control circuit, and the energy storage circuit is configured to store a voltage. The switch control circuit is configured to control the second end of the energy storage circuit to be electrically coupled to a voltage application end or the first end of the driving circuit under the control of a light-emission control signal from a light-emission control line. The driving circuit is configured to generate a driving current in accordance with a voltage between the control end and first end of the driving circuit.

Abstract: An electroluminescent display panel includes a plurality of repeating units each including a first conductive layer, a first insulating layer including a first via hole, and an anode including a main body and an auxiliary portion. At least one repeating unit includes a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel; the area of the main body of the third-color sub-pixel is larger than that of the second-color sub-pixel and that of the first-color sub-pixel; and an overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the second-color sub-pixel and the first conductive layer, and the overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the first-color sub-pixel and the first conductive layer.

Abstract: The present disclosure provides a pixel circuit, a pixel driving method, a display panel and a display device. The pixel circuit includes a light-emitting element, a driving circuitry, a first energy storage circuitry, a second energy storage circuitry, a data writing circuitry and a compensation circuitry. The data writing circuitry is configured to write a data voltage into a first end of the first energy storage circuitry under the control of a gate driving signal provided by a gate line. The compensation circuitry is configured to control a control end of the driving circuitry to be electrically coupled to a second end of the driving circuitry under the control of a compensation control signal. The driving circuitry is configured to generate a driving current for driving the light-emitting element under the control of a potential at its control end.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate according to an embodiment of the present disclosure includes: a base substrate, and a plurality of pixel units located on the base substrate; each pixel unit at least includes a driving transistor and a light-emitting device; the array substrate further includes: a shielding layer located between a layer where a gate of a driving transistor in each of the pixel units is located and a layer where a first electrode of the light-emitting device is located.

Abstract: A stretchable display panel, a method for compensating a threshold voltage of a transistor in the stretchable display panel, and a computer readable storage medium. The stretchable display panel includes: a base substrate; a transistor on the base substrate, the transistor includes a gate electrode layer and an active layer that are at least partially stacked; and a voltage compensation layer, the voltage compensation layer is located between the transistor and the base substrate, wherein the voltage compensation layer is applied with a compensation voltage that depends on a stretching amount of the stretchable display panel.

Abstract: A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.

Abstract: A pixel driving circuit includes a reset sub-circuit, a compensation sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The reset sub-circuit is configured to transmit an initialization signal received from an initialization signal terminal to the light-emitting control sub-circuit. The fight-emitting control sub-circuit is configured to transmit the initialization signal to the first node. The compensation sub-circuit is configured to transmit the initialization signal from the first node to a second node so as to reset a voltage of the second node. The driving sub-circuit is configured to open a conductive path from a first voltage signal terminal to the initialization signal terminal during a process of resetting the voltage of the second node.

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Abstract: A flexible array substrate includes at least one stretchable region; wherein the flexible array substrate is provided with a plurality of through holes within the stretchable region, and the plurality of through holes divide the stretchable region into a pixel island area for displaying and a bridging area for signal transmission; the bridging area includes a source-drain bridging area. The flexible array substrate, in the source-drain bridging area, includes: a base substrate, a first source-drain metal layer, a first insulating material layer, a second source-drain metal layer, a second insulating material layer, and an encapsulation layer that are sequentially stacked.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a first reference voltage line, a second reference voltage line and a first reference voltage auxiliary line, the first reference voltage line, the second reference voltage line and the first reference voltage auxiliary line are respectively disposed in one of a second wiring layer, a third wiring layer and a fourth wiring layer, the first reference voltage line is electrically coupled to the first reference voltage auxiliary line through via holes penetrating an insulating layer therebetween, the first reference voltage line and the first reference voltage auxiliary line extend in different directions, the second reference voltage line and the first reference voltage auxiliary line extend in a same direction, the first reference voltage line extends in a row or column direction, and the second reference voltage line extends in the row or column direction.

Abstract: A method may include obtaining various well logs or various core samples regarding a geological region of interest. The method may further include determining various permeability values, various porosity values, and various dolomite volume fraction values regarding the geological region of interest using the well logs or the core samples. The dolomite volume fraction values may correspond to a percentage of dolomite in a total mineral volume. The method may further include determining, using the porosity values, various permeability thresholds corresponding to various predetermined reservoir qualities. The method may further include generating, using the permeability thresholds, the permeability values, and the dolomite volume fraction values, a reservoir model including various dolomite boundaries defining the predetermined reservoir qualities. The method may further include determining a hydrocarbon trap prediction using the reservoir model.

Abstract: A pixel driving circuit includes a first thin film transistor having a double-gate structure, a conductive layer and a second thin film transistor. The first thin film transistor includes a first active layer. The first active layer includes a first and second semiconductor portions and a conductor portion located therebetween. The conductor portion has a first doping concentration. The conductive layer is at least partially opposite to the conductor portion, so that the conductive layer and the conductor portion form a capacitor. The conductive layer is configured to electrically connect to an initial voltage terminal. The second thin film transistor includes a second active layer and a first gate. A portion of the second active layer directly opposite to the first gate has a second doping concentration, and the second doping concentration is lower than the first doping concentration.

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

Abstract: A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.

Abstract: The disclosure relates to the technical field of alloys, and in particular to a titanium alloy with a gradient microstructure and a preparation method thereof Two new gradient microstructures different from the existing microstructure in titanium alloy are designed for the first time by an ingenious three-step heat treatment scheme, specifically, the gradient lamellar microstructure and gradient tri-modal microstructure. Compared with the regular uniform lamellar microstructure, the titanium alloy with gradient lamellar microstructure can achieve the simultaneous improvement of strength and ductility. Compared with the regular bimodal microstructure, the strength of a titanium alloy with a gradient tri-modal microstructure can be increased by about 10%, and the ductility is slightly reduced.

Abstract: A display panel includes: a base, a first electrode, a pixel definition layer and a first light-emitting functional layer. The first electrode is disposed on a side of the base; the pixel definition layer is disposed on the side of the base, and includes a first hollowed-out portion; the first hollowed-out portion includes a first opening and a second opening arranged oppositely, the first opening is closer to the base than the second opening, and the first opening exposes at least part of the first electrode; and the first light-emitting functional layer is disposed on sides of the pixel definition layer and the first electrode away from the base, and includes a second hollowed-out portion; an orthogonal projection of the second hollowed-out portion on the base is non-overlapping with an orthogonal projection of the first opening on the base.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a non-stretchable display region and a stretchable display region. The stretchable display region includes multiple island regions in an array and separated from each other, and multiple bridge regions connecting adjacent island regions, a pixel unit is arranged on each of the island regions, the pixel unit includes at least one pixel, and a signal wire electrically connecting the pixels is arranged on each bridge region. A pixel pitch between the pixels in the pixel unit in a stretching direction is a reference pitch P0, a pitch between two adjacent pixel units in the stretching direction is a first pitch P1, and the first pitch P1 is less than the reference pitch P0.

Abstract: A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.