Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.

Abstract: A memory module includes a memory module copy engine for copying data from an active memory die to a spare memory die. Access is mapped away from the active memory die to the spare memory die.

Abstract: A refresh rate of a random-access memory (RAM) is increased if a number of errors is greater than an error threshold and the refresh rate has not reached a maximum rate. The refresh rate of the RAM is set to a normal rate if the number of errors is less than or equal to the error threshold.

Abstract: An access of data in a memory device is sampled. In response to the sampled access of data, a refresh operation is performed in the memory device.

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: Examples disclosed herein relate to determining whether a right to use memory modules in a reliability mode has been acquired. Examples include determining whether the right to use a plurality of memory modules in a reliability mode has been acquired, if a performance mode is selected for operation of the plurality of memory modules.

Abstract: A memory module includes a memory module copy engine for copying data from an active memory die to a spare memory die. Access is mapped away from the active memory die to the spare memory die.

Abstract: A computer-implemented method for increasing a number of ranks per channel. The channel comprises at least one buffered dual in-line memory module (DIMM). The at least one buffered DIMM comprises a conventional number of ranks and a conventional number of pins. The method includes receiving a memory access request at a memory controller, wherein the memory controller comprises a conventional number of pins. The method also includes encoding a plurality of chip-select (CS) signals at the memory controller, wherein the plurality of CS signals are based on the memory access request, such that the number of ranks per channel increases compared to a conventional number of ranks per channel while not requiring an increase in the number of pins in the memory controller compared to the conventional number of pins of the memory controller.

Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.

Abstract: A translator of an apparatus in an example through a serial connection external interface of a printed circuit board (PCB) communicates between a serial memory protocol within the PCB and a parallel memory protocol outside the PCB.

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.

Abstract: A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported.

Abstract: A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).

Abstract: Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

Abstract: A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch.