Abstract: Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

Abstract: A translator of an apparatus in an example employs a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) to write to a plurality of parallel protocol memory module channels that comprises a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported.

Abstract: A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch.

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: A computer system includes a printed circuit board (PCB) that includes a first external interface for memory connection thereto, the first external interface employs a first memory protocol. The computer system further includes an extension circuit board and a translator module. the extension circuit board includes a second external interface for memory connection thereto and a third external interface, wherein the second external interface employs a second memory protocol different from the first memory protocol. The translator module is connectable to the first external interface of the PCB and the third external interface of the extension circuit board to provide translation between the first and second memory protocols.

Abstract: A translator of an apparatus in an example through a serial connection external interface of a printed circuit board (PCB) communicates between a serial memory protocol within the PCB and a parallel memory protocol outside the PCB.

Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.

Abstract: Attachment mechanisms are surface-mounted to a PC board. An object is secured relative to said PC board by a retention device attached to the attachment mechanisms.

Abstract: A stencil for the deposition of a heat yieldable joining material includes at least one pattern formation member and at least one channel formation portion associated with the pattern formation member.

Abstract: A circuit and system addressing multiple computer memory modules on the same bus while maintaining proper timing. The circuit includes a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches from the branch point. Individual branches are coupled to at least one memory module interface.