Patents by Inventor Lidong Xu
Lidong Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078630Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: ApplicationFiled: October 19, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Publication number: 20240080472Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.Type: ApplicationFiled: September 18, 2023Publication date: March 7, 2024Applicant: Tahoe Research, Ltd.Inventors: Yi-Jen CHIU, Lidong XU, Hong JIANG
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Patent number: 11861761Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: GrantFiled: November 11, 2020Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Publication number: 20230418617Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.Type: ApplicationFiled: June 22, 2023Publication date: December 28, 2023Applicant: INTEL CORPORATIONInventors: Christopher J. HUGHES, Prasoonkumar SURTI, Guei-Yuan LUEH, Adam T. LAKE, Jill BOYCE, Subramaniam MAIYURAN, Lidong XU, James M. HOLLAND, Vasanth RANGANATHAN, Nikos KABURLASOS, Altug KOKER, Abhishek R. Appu
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Publication number: 20230401807Abstract: Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.Type: ApplicationFiled: August 28, 2023Publication date: December 14, 2023Applicant: Tahoe Research, Ltd.Inventors: Ke CHEN, Zhipin DENG, Xiaoxia CAI, Chen WANG, Ya-Ti PENG, Yi-Jen CHIU, Lidong XU
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Publication number: 20230377209Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.Type: ApplicationFiled: May 23, 2023Publication date: November 23, 2023Applicant: Intel CorporationInventors: ABHISHEK R. APPU, PRASOONKUMAR SURTI, JILL BOYCE, SUBRAMANIAM MAIYURAN, MICHAEL APODACA, ADAM T. LAKE, JAMES HOLLAND, VASANTH RANGANATHAN, ALTUG KOKER, LIDONG XU, NIKOS KABURLASOS
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Patent number: 11765380Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.Type: GrantFiled: November 30, 2020Date of Patent: September 19, 2023Assignee: Tahoe Research, Ltd.Inventors: Yi-Jen Chiu, Lidong Xu, Hong Jiang
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Patent number: 11741682Abstract: Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.Type: GrantFiled: July 29, 2021Date of Patent: August 29, 2023Assignee: Tahoe Research, Ltd.Inventors: Ke Chen, Zhipin Deng, Xiaoxia Cai, Chen Wang, Ya-Ti Peng, Yi-Jen Chiu, Lidong Xu
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Publication number: 20230260075Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Patent number: 11729416Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2017Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Srinivasan Embar Raghukrishnan, James M. Holland, Sang-Hee Lee, Atthar H. Mohammed, Dmitry E. Ryzhov, Jason Tanner, Lidong Xu, Wenhao Zhang
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Patent number: 11726793Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.Type: GrantFiled: November 11, 2020Date of Patent: August 15, 2023Assignee: INTEL CORPORATIONInventors: Christopher J. Hughes, Prasoonkumar Surti, Guei-Yuan Lueh, Adam T. Lake, Jill Boyce, Subramaniam Maiyuran, Lidong Xu, James M. Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Abhishek R. Appu
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Patent number: 11663746Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.Type: GrantFiled: November 11, 2020Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Abhishek R. Appu, Prasoonkumar Surti, Jill Boyce, Subramaniam Maiyuran, Michael Apodaca, Adam T. Lake, James Holland, Vasanth Ranganathan, Altug Koker, Lidong Xu, Nikos Kaburlasos
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Patent number: 11616968Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.Type: GrantFiled: November 10, 2020Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Zhipin Deng, Iole Moccagatta, Lidong Xu, Wenhao Zhang, Yi-Jen Chiu
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Publication number: 20230054523Abstract: An example apparatus for enhancing video includes a decoder to decode a received 360-degree projection format video bitstream to generate a decoded 360-degree projection format video. The apparatus also includes a viewport generator to generate a viewport from the decoded 360-degree projection format video. The apparatus further includes a convolutional neural network (CNN)-based filter to remove an artifact from the viewport to generate an enhanced image. The apparatus further includes a displayer to send the enhanced image to a display.Type: ApplicationFiled: February 17, 2020Publication date: February 23, 2023Inventors: Huan Dou, Lidong Xu, Xiaoxia Cai, Chen Wang, Yi-Jen Chiu
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Publication number: 20230052483Abstract: An apparatus for super resolution imaging includes a convolutional neural network (104) to receive a low resolution frame (102) and generate a high resolution illuminance component frame. The apparatus also includes a hardware scaler (106) to receive the low resolution frame (102) and generate a second high resolution chrominance component frame. The apparatus further includes a combiner (108) to combine the high resolution illuminance component frame and the high resolution chrominance component frame to generate a high resolution frame (110).Type: ApplicationFiled: February 17, 2020Publication date: February 16, 2023Inventors: Xiaoxia Cai, Chen Wang, Huan Dou, Yi-Jen Chiu, Lidong Xu
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Publication number: 20220417559Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. In an example encoder, first circuitry is to encode video input data into a bitstream according to a bitstream syntax, wherein the video input data includes one or more pictures, the one or more pictures are partitioned into one or more coding tree blocks, the one or more coding tree blocks are partitioned into slices including one or more coding tree blocks, the one or more coding tree blocks include one or more transform blocks according to a transform tree including a split_transform_flag indicative of the split of a given coding block into corresponding one or more transform blocks, the split_transform_flag is coded using CABAC, and a context index associated with the CABAC coding of the split_transform_flag is based on a value. Second circuitry of the encoder is to output the bitstream.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Wenhao Zhang, Yi-Jen Chiu, Pieter Kapsenberg, Lidong Xu, Yu Han, Zhipin Apple Deng, Xiaoxia Cai
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Publication number: 20220351496Abstract: A method for image content classification is described herein. The method includes counting a number of distinct color numbers in an image. The method also includes clustering blocks with a same distinct color number into a same class and determining a block occupancy rate of each color number for the image. Finally, the method includes classifying the image according to the block occupancy rate via a plurality of classifiers communicatively coupled in series.Type: ApplicationFiled: December 24, 2019Publication date: November 3, 2022Inventors: Huan DOU, Lidong XU, Xiaoxia CAI, Chen WANG, Yi-Jen CHIU
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Patent number: 11432011Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation.Type: GrantFiled: December 14, 2020Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Wenhao Zhang, Yi-Jen Chiu, Pieter Kapsenberg, Lidong Xu, Yu Han, Zhipin Apple Deng, Xiaoxia Cai
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Publication number: 20220174304Abstract: Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 23, 2020Publication date: June 2, 2022Inventors: Jill Boyce, Lidong Xu
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Patent number: 11328496Abstract: Systems, apparatus, articles, and methods are described below including operations for scalable real-time face beautification of video images.Type: GrantFiled: October 21, 2019Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Ke Chen, Zhipin Deng, Xiaoxia Cai, Chen Wang, Ya-Ti Peng, Yi-Jen Chiu, Lidong Xu