Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Abstract: A thin film transistor and a preparation method thereof, a display panel, and a display device. The thin film transistor includes an active structure and a gate that are stacked and insulated by an interlayer insulating layer, the active structure includes a source region, a drain region, and a channel region, the source region and the drain region are located on two sides of the channel region, and in a thickness direction of the interlayer insulating layer, a projection of the gate overlaps with a projection of the channel region; wherein the channel region includes a metal oxide material, a ratio of a number of indium atoms and a number of zinc atoms in the channel region is a, and a?4.

Abstract: Disclosed is a clamping device having an automatic direction adjustment function in a vehicle body welding conveying line, including a conveying frame. A driving motor is fixedly connected to a side wall of the conveying frame, and an output shaft end of the driving motor is fixedly connected to a rotating shaft I. The present disclosure facilitates the adjustment of a direction when vehicle bodies to be welded are conveyed on a turning conveying line, and vehicle bodies being conveyed can be corrected to the same horizontal state, to avoid a situation where the clamping device on the conveying line cannot smoothly clamp inclined vehicle bodies for conveying because the vehicle bodies cannot be in the same horizontal plane when being put in.

Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation. In an example encoder, first circuitry is to encode video input data into a bitstream according to a bitstream syntax, wherein the video input data includes one or more pictures, the one or more pictures are partitioned into one or more coding tree blocks, the one or more coding tree blocks are partitioned into slices including one or more coding tree blocks, the one or more coding tree blocks include one or more transform blocks according to a transform tree including a split_transform_flag indicative of the split of a given coding block into corresponding one or more transform blocks, the split_transform_flag is coded using CABAC, and a context index associated with the CABAC coding of the split_transform_flag is based on a value. Second circuitry of the encoder is to output the bitstream.

Abstract: The present disclosure relates to a wind farm layout and yaw control method, and an electronic device. The wind farm layout and yaw control method comprises the following steps: acquiring wind farm data, importing the wind farm data into a WFSim model for simulation, obtaining original power data of the wind farm, counting and recording modifiable wind farm layout and yaw parameters, adjusting variable parameters to be changed, using the WFSim model for simulation to obtain an optimal parameter range of different variables and combining the optimal parameters to obtain an optimal working condition, and using the WFSim model for simulation to obtain optimal power data. The wind farm layout and yaw control method according to the present disclosure is based on optimizing the power output of the wind farm, so that it is very convenient to acquired information.

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Abstract: An example apparatus for enhancing video includes a decoder to decode a received 360-degree projection format video bitstream to generate a decoded 360-degree projection format video. The apparatus also includes a viewport generator to generate a viewport from the decoded 360-degree projection format video. The apparatus further includes a convolutional neural network (CNN)-based filter to remove an artifact from the viewport to generate an enhanced image. The apparatus further includes a displayer to send the enhanced image to a display.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to determine confidence of motion vectors. Examples disclosed herein are to generate feature data associated with a motion vector, the motion vector generated based on a first block of pixel data in a first video frame and a second block of pixel data in a second video frame, determine a confidence score for the motion vector based on a model and the feature data, and concatenate the motion vector and the confidence score to output an estimated likelihood that the motion vector is accurate.

Abstract: Disclosed examples populate a supplemental enhancement information (SEI) message with a value corresponding to a number of subpictures of a video sequence; populate a level indicator in the SEI message; populate a subpicture identifier; populate the subpicture identifier in a slice header, and cause the SEI message and the slice header to be included in a video bitstream.

Abstract: Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.

Abstract: A method, system, and article is directed to automatic content-dependent image processing algorithm selection.

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Systems, apparatus, articles of manufacture and methods for face augmentation in video are disclosed. An example apparatus includes executable code to detect a face of a subject in the video, detect a gender of the subject based on the face, detect a skin tone of the subject based on the face, apply a first process to smooth skin on the face in the video, apply a second process to change the skin tone of the face, apply a third process to slim the face, apply a fourth process to adjust a size of eyes on the face, and apply a fifth process to remove an eye bag from the face. One or more of the first process, the second process, the third process, the fourth process, or the fifth process adjustable based on one or more of the gender or an age. The example apparatus also includes one or more processors to generate modified video with beauty effects, the beauty effects based on one or more of the first process, the second process, the third process, the fourth process, or the fifth process.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.