Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Abstract: Enhanced processor functions for calculation are described. An example of an apparatus includes one or more processors including one or more processing resources and a memory to store data, the data including data for compute operations. A processing resource of the one or more processing resources includes a configurable pipeline for calculation operations, and wherein the configurable pipeline may be utilized to perform both a normal instruction for a calculation in a certain precision and a systolic instruction for a calculation in a certain precision.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Abstract: In a scalable video codec, an adaptive Wiener filter with offset aims to minimize the differences between two input pictures or picture regions, and the filter coefficients need to be transmitted to decoder site.

Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Abstract: Systems, apparatus, articles, and methods are described including operations for size based transform unit context derivation.

Abstract: Techniques related to motion estimation with neighbor block pattern for video coding.

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

Abstract: Techniques related to video coding with context decoding and reconstruction bypass.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

Abstract: Systems, devices and methods are described including performing scalable video coding using inter-layer residual prediction. Inter-layer residual prediction in an enhancement layer coding unit, prediction unit, or transform unit may use residual data obtained from a base layer or from a lower enhancement layer. The residual may be subjected to upsample filtering and/or refinement filtering. The upsample or refinement filter coefficients may be predetermined or may be adoptively determined.

Abstract: Systems, apparatus and methods are described including determining a prediction residual for a channel of video data; and determining, using the first channel's prediction residual, a prediction residual for a second channel of the video data. Further, a prediction residual for a third channel of the video data may be determined using the second channel's prediction residual.

Abstract: Systems, apparatus, articles, and methods are described below including operations for scalable real-time face beautification of video images.

Abstract: Systems, apparatus and methods are described including operations for video coding including cross-layer cross-channel residual prediction.

Abstract: Methods, systems, and computer program products for the generation of multiple layers of scaled encoded video data compatible with the HEVC standard. Residue from prediction processing may be transformed into coefficients in the frequency domain. The coefficients may then be sampled to create a layer of encoded data. The coefficients may be sampled in different ways to create multiple respective layers. The layers may then be multiplexed and sent to a decoder. There, one or more of the layers may be chosen. The choice of certain layer(s) may be dependent on the desired attributes of the resulting video. A certain level of video quality, frame rate, resolution, and/or bit depth may be desired, for example. The coefficients in the chosen layers may then be assembled to create a version of the residue to be used in video decoding.

Abstract: Embodiments are generally directed to affine motion compensation for current picture referencing. An embodiment of an apparatus includes one or more processors for processing of data; a memory for storage of data including video data; and an encoder for encoding of video data to generate encoded video data, wherein the encoder includes a component to provide affine motion compensation for current picture references in the video data.