Patents by Inventor Lien-Yao TSAI
Lien-Yao TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11513287Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.Type: GrantFiled: July 13, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kai-Fung Chang, Lien-Yao Tsai, Chien Shih Tsai, Shih-Che Hung
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Publication number: 20220289564Abstract: A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Patent number: 11345591Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.Type: GrantFiled: December 16, 2019Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
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Patent number: 11062903Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.Type: GrantFiled: October 26, 2018Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Neena Avinash Gilda, Lien-Yao Tsai, Baohua Niu
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Patent number: 10981779Abstract: A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.Type: GrantFiled: March 2, 2018Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
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Patent number: 10865100Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.Type: GrantFiled: June 21, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
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Patent number: 10861929Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.Type: GrantFiled: October 18, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Fung Chang, Lien-Yao Tsai, Baohua Niu, Yi-Chuan Teng, Chi-Yuan Shih
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Publication number: 20200341192Abstract: The present disclosure provides a waveguide structure including an optical component. The optical component includes a plurality of grating coupler teeth over a semiconductive substrate and a plurality of grating coupler openings between adjacent grating coupler teeth, wherein the grating coupler openings are configured to receive a light wave. Each of the grating coupler teeth includes a dielectric stack and an etch stopper embedded in the dielectric stack, wherein the etch stopper has a resistance to a fluorine solution that is higher than that of the dielectric stack. A method of manufacturing a semiconductor device is also provided.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: KAI-FUNG CHANG, LIEN-YAO TSAI, CHIEN SHIH TSAI, SHIH-CHE HUNG
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Patent number: 10777733Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A voltage is applied to the intermediate layer. A unit cell of the intermediate layer is stretched or compressed by the voltage. The polarity of the intermediate layer is changed by the voltage.Type: GrantFiled: November 28, 2018Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Neena Avinash Gilda, Lien-Yao Tsai, Baohua Niu
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Patent number: 10712500Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.Type: GrantFiled: October 17, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kai-Fung Chang, Lien-Yao Tsai, Chien Shih Tsai, Shih-Che Hung
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Publication number: 20200168789Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A voltage is applied to the intermediate layer. A unit cell of the intermediate layer is stretched or compressed by the voltage. The polarity of the intermediate layer is changed by the voltage.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Inventors: NEENA AVINASH GILDA, LIEN-YAO TSAI, BAOHUA NIU
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Publication number: 20200135446Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Neena Avinash GILDA, Lien-Yao TSAI, Baohua NIU
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Publication number: 20200124790Abstract: The present disclosure provides a semiconductor device, including a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate to form a wall of a grating coupler opening, and an etch stopper interfacing with two sublayers of the dielectric stack and partially separating the interface of the two sublayers. The etch stopper has a resistance to a fluorine solution that is higher than that of the two sublayers. A method of manufacturing the semiconductor device is also provided.Type: ApplicationFiled: October 17, 2018Publication date: April 23, 2020Inventors: KAI-FUNG CHANG, LIEN-YAO TSAI, CHIEN SHIH TSAI, SHIH-CHE HUNG
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Publication number: 20200115223Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Publication number: 20200006470Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.Type: ApplicationFiled: October 18, 2018Publication date: January 2, 2020Inventors: Kai-Fung CHANG, Lien-Yao TSAI, Baohua NIU, Yi-Chuan TENG, Chi-Yuan SHIH
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Patent number: 10508028Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: GrantFiled: December 4, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
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Publication number: 20190315620Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a substrate over a micro-electro-mechanical system (MEMS) substrate. The substrate includes a semiconductor via. The method also includes forming a dielectric layer over a top surface of the substrate, and forming a polymer layer over the dielectric layer. The method further includes patterning the polymer layer to form an opening, and the semiconductor via is exposed by the opening. The method includes forming a conductive layer in the opening and over the polymer layer, and forming an under bump metallization (UBM) layer on the conductive layer. The method further includes forming an electrical connector over the UBM layer, wherein the electrical connector is electrically connected to the semiconductor via through the UBM layer.Type: ApplicationFiled: June 21, 2019Publication date: October 17, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Fung CHANG, Lien-Yao TSAI, Len-Yi LEU
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Patent number: 10343895Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The MEMS device structure includes a micro-electro-mechanical system (MEMS) substrate, and a substrate formed over the MEMS substrate. The substrate includes a semiconductor via through the substrate. The MEMS device structure includes a dielectric layer formed over the substrate and a polymer layer formed on the dielectric layer. The MEMS device structure also includes a conductive layer formed in the dielectric layer and the polymer layer. The conductive layer is electrically connected to the semiconductor via, and the polymer layer is between the conductive layer and the dielectric layer.Type: GrantFiled: February 14, 2018Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
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Patent number: 10266400Abstract: Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also includes a cap bonded to the first substrate, where the cap and the first substrate define a first sealed cavity and a second sealed cavity. The first conductive feature and the first movable element are disposed in the first sealed cavity and the second conductive feature and the second movable element are disposed in the second sealed cavity. A pressure of the second cavity is higher than a pressure of the first sealed cavity, and an out gas layer is disposed in a recess of the cap that partially defines the second sealed cavity.Type: GrantFiled: September 18, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung Chang, Len-Yi Leu, Lien-Yao Tsai
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Publication number: 20190112184Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: ApplicationFiled: December 4, 2018Publication date: April 18, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU