Abstract: A temperature fuse assembly for a high-power DC circuit is provided. The temperature fuse assembly includes a case extending from a first case end to a second case end and an isolated lead projecting from the second case end. A bushing electrically isolates the isolated lead from the case. A high-gauge wire is electrically connected to the case at a first wire end and electrically connected to the isolated lead at a second wire end. A portion of the high-gauge wire is helically wound about an exterior of the bushing. When a temperature of the temperature fuse assembly exceeds a threshold temperature, the temperature fuse assembly is configured to conduct a DC current of the high-power DC circuit through the high-gauge wire. The high-gauge wire is configured to melt under a load of the DC current and interrupt the high-power DC circuit.

Abstract: An electronic device includes a wristband comprising a first main surface and a second main surface disposed oppositely; a first display panel and a second display panel which are disposed on the wristband and at least partially facing each other. The first display panel is disposed on the first main surface and the second display panel is a flexible display panel and disposed on the second main surface.

Abstract: An electronic device includes a wristband comprising a first main surface and a second main surface disposed oppositely; a first display panel and a second display panel which are disposed on the wristband and at least partially facing each other. The first display panel is disposed on the first main surface and the second display panel is a flexible display panel and disposed on the second main surface.

Abstract: A craft punch with a replaceable cutting tool includes a main body having an upper part and a lower part which are spaced up and down. The upper part has a passage, and the lower part has a receiving part to movably receive a lower cutting mold holder. An upper cutting mold holder receiving component could be installed in the passage movably up and down, the upper side of the receiving component bulges to form a tubular part, and one side of the receiving component back to the tubular part is provided with a receiving part which could movably receive an upper cutting mold; a cover plate covers the upper end of the passage and is provided with a through hole allowing the tubular part to pass through an upper bulge, and an upper cover covers the upper side of the cover plate, and is connected with the tubular part.

Abstract: Disclosed is exposure machine, comprising: a loading frame, for placing an object to be exposed; a light source device, located at one side of a plane where the loading frame is positioned, wherein the light emitting direction of the light source device is perpendicular to a plane where the object to be exposed is positioned. During exposure, the loading frame will not reflect the light transmitting through the object to be exposed, and thus the stage spots are avoided. Further, when the exposure machine is operated in a vertical manner, a bidirectional exposure may be achieved only by adding a single prism into the light source device in the prior art, and thus the exposure efficiency is greatly improved.

Abstract: Disclosed is exposure machine, comprising: a loading frame, for placing an object to be exposed; a light source device, located at one side of a plane where the loading frame is positioned, wherein the light emitting direction of the light source device is perpendicular to a plane where the object to be exposed is positioned. During exposure, the loading frame will not reflect the light transmitting through the object to be exposed, and thus the stage spots are avoided. Further, when the exposure machine is operated in a vertical manner, a bidirectional exposure may be achieved only by adding a single prism into the light source device in the prior art, and thus the exposure efficiency is greatly improved.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1?yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1?yGey, and strained Si1?yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1?yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1?yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1?yGey, and strained Si1?yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1?yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly seletive etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts of the SiGe/Si heterojunction diodes.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.

Abstract: A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 rpm, a crarrier speed of 30 rpm and a slurry flow rate of 140 milliliters per minute.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.