LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS
A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
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This application is a divisional application of U.S. patent application Ser. No. 10/948,421, filed Sep. 23, 2004, which is a divisional of U.S. patent application Ser. No. 09/692,606 filed on Oct. 19, 2000, which later issued as U.S. Pat. No. 6,890,835 on May 10, 2005 and as such, claims priority from both Ser. No. 09/692,606 and U.S. Pat. No. 6,890,835.
FIELD OF INVENTIONThis invention relates to transferring a SiGe layer onto a second substrate and forming a new material structure that has emerging applications in microelectronics and optoelectronics. In particular, a strained Si/SiGe layer on an insulator structure is useful for fabricating high speed devices such as complementary metal oxide semiconductor (CMOS) transistors, modulation doped field effect transistors (MODFETs), high electron mobility transistors (HEMTs), and bipolar transistors (BTs); SiGe layer on Si heterostructures can be used to produce photodetectors to provide Si-based far infrared detection for communication, surveillance and medical applications.
BACKGROUND OF THE INVENTIONFor applications in microelectronics, high carrier mobilities are desirable. It has been found that electron mobility in strained Si/SiGe channels is significantly higher than that in bulk Si. For example, measured values of electron mobility in strained Si at room temperature are about 3000 cm2/Vs as opposed to 400 cm2/Vs in bulk Si. Similarly, hole mobility in strained SiGe with high Ge concentration (60%˜80%) reaches up to 800 cm2/Vs the value of which is about 5 times the hole mobility of 150 cm2/Vs in bulk Si. The use of these materials in state-of-the-art Si devices is expected to result in much higher performances, higher operating speeds in about 5 times the hole mobility of 150 cm2/Vs in bulk Si. The use of these materials in state-of-the-art Si devices is expected to result in much higher performances, higher operating speeds in particular. However, the underlying conducting substrate for MODFETs and HBTs or the interaction of the underlying substrate with active device region in CMOS are undesirable features which limit the full implementation of high speed devices. To resolve the problem, an insulating layer is proposed to isolate the SiGe device layer from the substrate. Therefore, there is a need for techniques capable of fabricating strained Si/SiGe on insulator materials.
There are two available techniques for making SiGe-On-Insulator (SGOI). One is via SIMOX as reported in a publication by T. Mizuno et al., entitled “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology,” IEDM, 99-934. However, this method has several limits because the oxygen implantation induces further damages in the relaxed SiGe layer in addition to the existing defects caused by lattice mismatch. And, the high temperature anneal (>1100° C.) needed to form oxide after the oxygen implantation is detrimental to the strained Si/SiGe layers since Ge tends to diffuse and agglomerate at temperatures above 600° C., this effect becomes more significant when Ge content is higher than 10%.
The second technique of making SiGe on insulator is via selective etching with the aid of an etch stop. In U.S. Pat. No. 5,906,951 by J. O. Chu and K. E. Ismail which issued in May 1999, a method of utilizing wafer bonding and backside wafer etching in KOH with a p++-doped SiGe etch-stop to transfer a layer of strained Si/SiGe on a SOI substrate was described. However, the etching selectivity of SiGe to p++-doped SiGe etch-stop in KOH decreases sharply as the doping level in the etch stop layer is below 1019/cm3, therefore, the strained Si/SiGe layer may also be subjected to KOH etching if etching could not stop uniformly at the p++ SiGe etch-stop layer due to variation of dopants in the p++ etch-stop layer. Furthermore, since the SiGe etch-stop layer is heavily doped with boron in the range from about 5×1019 to about 5×1020/cm3, there are chances of auto-doping of the strained Si/SiGe during thermal treatment.
For fiber optic applications, SiGe/Si heterojunction diodes are a good choice for demodulating 1.3-1.6 um light at 300K. The use of 30% to 50% Ge is suggested to achieve absorption at the desired 1.3-1.6 um wavelength and low defects such as dislocations in the SiGe layer is needed to enhance the photodetector sensitivity. The state-of-the-art technology to achieve SiGe/Si heterojunction diodes with high responsitivity, low noise, and fast response is to form a 100-period SiGe/Si strained layer superlattice. However, the alloy then no longer behaves like the bulk material due to the quantum size effect. The net result of the quantum size effect is that the absorption occurs at wavelengths (1.1-1.3 um) shorter than expected. Therefore, a bulk SiGe alloy with desirable Ge content and low defects is needed to fabricate photodetectors that would absorb lights in the range of 1.3-1.6 um.
The invention provides a method capable of transferring a low defect SiGe layer onto a desirable substrate using the etch-back method but without any additional heavily doped etch-stop layer. The key feature of this invention is that a SiGe layer serves both as the layer over which the epitaxial strained Si/SiGe is grown but also as an etch-stop layer itself in some specific etching solutions. In other words, the SiGe layer is a self-etch-stop in this case. As a result, the process of fabricating strained Si/SiGe on insulator or a SiGe/Si heterostructure is greatly simplified and the quality of the strained Si/SiGe or SiGe/Si heterostructure is significantly improved.
SUMMARY OF THE INVENTIONIn accordance with the present invention, a method for transferring low defect SiGe bulk layer onto a second substrate and forming strained Si/SiGe on an insulator (SGOI) or SiGe/Si heterostructure is described. This approach comprises the steps of selecting a semiconductor substrate, forming a first expitaxial graded layer of Si1-xGex over the semiconductor substrate, forming a second relaxed Si1-yGey over the first graded Si1-xGex layer, selecting a second substrate, bonding the first substrate to said second substrate to form a joined substrate, grinding and polishing the first substrate from its backside to remove the majority of said first substrate, etching the remaining material of the first substrate and stopping at the Si1-xGex utilizing a SiGe highly selective wet etch process, applying chemical-mechanical planarization (CMP) to remove the defective portion of the graded Si1-xGex layer, smoothing the surface of the Si1-xGex layer by a CMP process step, growing strained Si/SiGe layers over the smoothed surface of the Si1-xGex layer for MOSFET, MODFET, HEMT or BT for microelectronic applications, or growing SiGe photodetectors for applications in optoelectronics.
The invention provides a method capable of transferring a low defect SiGe layer onto a desirable substrate using the etch-back method but without any additional heavily doped etch-stop layer. The key feature of this invention is that a SiGe layer serves both as the layer over which the epitaxial strained Si/SiGe is grown but also as an etch-stop layer itself in some specific etching solutions. In other words, the SiGe layer is a self-etch-stop in this case. As a result, the process of fabricating strained Si/SiGe on insulator or a SiGe/Si heterostructure is greatly simplified and the quality of the strained Si/SiGe or SiGe/Si heterostructure is significantly improved.
The invention is described in more details thereinafter relative to non-limitative embodiments and with reference to the attached drawings, wherein show:
The embodiments which will now be described in conjunction with the above drawings relate[[s]] to the formation of a layer of monocrystalline strained Si/SiGe on an insulator material (SGOI) or a SiGe layer on Si with the aid of planarization of surfaces, wafer bonding and a selective wet etching process using SiGe as the etch-stop layer. Figures with a labeling suffix of A refer to the first embodiment of the present invention; those with a labeling suffix B refer to the second embodiment of the present invention; those with a labeling suffix C refer to the second embodiment of the present invention. All three embodiments are described in parallel in the description of the present invention.
Referring now to
Epitaxial layer 30 is comprised substantially or completely of relaxed Si1-yGey and is formed on upper surface 22 of layer 20. Layer 30 may have a thickness in the range from 200 nm to 1000 nm. The Ge content y in layer 30 is chosen to match the crystal lattice constant of upper surface 22 of layer 20 such that layer 30 is relaxed or essentially strain free. The Ge content y in layer 30 may be equal to or about the value of x at upper surface 22. The value y may be in the range from about 0.2 to about 0.5. An encapsulation layer 40 may be formed over relaxed layer 30. According to the first and third embodiments, an encapsulation layer 40 is not formed. According to the second embodiment, an encapsulation layer 40 is formed. Encapsulation layer 40 may be formed on upper surface 32 of layer 30 via PECVD, LPCVD, UHV CVD or spin-on techniques. Encapsulation layer 40 may have an upper surface 42. The encapsulation material may be, for example, Si, SiO2, Poly Si, Si3N4, low-k dielectric materials, for example, Diamond Like Carbon (DLC), Fluorinated Diamond Like Carbon (FDLC), a polymer of Si, C, O, and H or a combination of any two or more of the foregoing materials. One example of a polymer of Si, C, O, and H is SiCOH which is described in Ser. No. 09/107,567 filed Jun. 29, 1998 by Grill et al., entitled “Hydrogenated Oxidized Silicon Carbon Material” (Docket YOR919980245US1) which is incorporated herein by reference. The deposition temperature for forming layer 40 may be below 900° C. The thickness of the encapsulation layer is in the range from about 5 nm to about 500 nm. Encapsulation layer 40 functions to protect upper surface 32 of layer 30 or to provide an isolation layer.
In
According to the first and second embodiments of the present invention, in
For a further description on polishing to reduce surface roughness, reference is made to Ser. No. 09/675,841 filed Sep. 29, 2000 by D. F. Canaperi et al., entitled “A Method of Wafer Smoothing for Bonding Using Chemo-Mechanical Polishing (CMP)” (Docket No. YOR920000683US1) which is incorporated herein by reference.
For a further description on bonding wafers to provide a bonded structure, reference is made to Ser. No. 09/675,840 filed Sep. 29, 2000 by D. F. Canaperi et al., entitled “Preparation of Strained Si/SiGe on Insulator by Hydrogen Induced Layer Transfer Technique” (Docket No. YOR920000345US1) which is incorporated herein by reference. The method of making SGOI by wafer bonding and H-implantation induced layer transfer is described in Ser. No. 09/675,840. This method can produce SiGe with higher Ge content onto an insulator compared to the prior art. Further, this method can reduce the amount of defects in the SiGe layer due to the elimination of the misfit dislocations compared to the prior art. However, with this method, the transferred SiGe layer is relatively thin (<1 um) and transferring a high Ge content layer is still difficult to achieve due to implantation of H and annealing at 500 to 600° C. to induce layer transfer
According to the second embodiment of the present invention, t[[T]]he top surface 42 of layer 40 shown in
In
It should be noted in the drawing that like elements or components are referred to by like and corresponding reference numerals.
While there has been described and illustrated a method for forming strained Si or SiGe on SiGe on insulator (SGOI) or strained SiGe/Si heterostructure using wafer bonding and wet etching, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.
Claims
1. A multi layer substrate for use in forming integrated circuits comprising:
- a silicon substrate, and
- a relaxed Si1-yGey layer on said silicon substrate, said relaxed Si1-yGey layer chemically bonded to said silicon substrate.
2. The multi layer substrate of claim 1 wherein said relaxed Si1-yGey layer has a buried lower surface roughness in the range from about 0.3 nm to about 1 nm RMS.
3. The multi layer substrate of claim 1 wherein said silicon substrate bonded to said relaxed Si1-yGey layer has a buried surface roughness in the range from about 0.3 nm to about 1 nm RMS.
4. The multi layer substrate of claim 1 wherein said relaxed Si1-yGey layer has a value y in the range from about 0.2 to about 0.5.
5. The multi layer substrate of claim 1 further including a strained epitaxial silicon containing layer on said relaxed Si1-yGey layer
Type: Application
Filed: Jul 29, 2008
Publication Date: Jan 29, 2009
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Jack Oon Chu (Manhasset Hills, NY), David R. DiMilia (Wappingers Falls, NY), Lijuan Huang (Tarrytown, NY)
Application Number: 12/181,489
International Classification: H01L 29/161 (20060101);