Abstract: A building control device includes a printed circuit board (PCB) assembly with a controller. A lighting assembly is operatively coupled to the PCB and is controlled by the controller. The lighting assembly includes a light guide that extends around a periphery of an interposing region. The light guide having a front face and one or more light sources optically coupled to the light guide such that light provided by the one or more light sources enters the light guide and is distributed to the front face of the light guide to provide a diffuse light output. A cover forms at least part of a front face of the building control device and includes a transparent region in registration with at least part of the front face of the light guide.

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

Abstract: Flexible under-bump metallization sizes and patterning, and related integrated circuit packages and fabrication methods are disclosed. First under-bump metallizations (UBMs) of a first, larger size and pitch are provided in the die and coupled to corresponding metal interconnects in the package substrate. One or more second UBMs of a second, reduced size UBMs can also be located in the core area of the die. This provides greater flexibility in the design and layout of the die, because different circuits within the die (e.g., I/O related circuits) may only require coupling to smaller size UBMs for performance requirements and thus can be more flexibility located in the die. Also, to further reduce pitch of the second, smaller size UBMs, one or more of the second, smaller size UBMs can be formed as oblong-shaped UBMs, which can still maintain a minimum separation based on metal interconnect pitch limitations in the package substrate.

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

Abstract: A device includes an integrated device. The integrated device includes a die that is at least partially encapsulated. The die includes a conductive pad. The device also includes a first passivation layer coupled to a first surface of the die. The device includes an offset interconnect extending along a surface of the first passivation layer and including a portion that extends through an opening in the first passivation layer to contact the conductive pad. The device includes a bump including a portion that extends through an opening in a second passivation layer to contact the offset interconnect. The bump is offset, in a direction along a surface of the second passive layer, from the conductive pad.

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Abstract: A building control device includes a printed circuit board including control circuitry for controlling at least part of the building control device. An LCD display is operatively coupled to the printed circuit board and is controlled at least in part by the control circuitry of the printed circuit board. A plurality of LEDs are operatively coupled to the printed circuit board and are controlled at least in part by the control circuitry of the printed circuit board. An opaque plate defines an at least translucent arc-shaped region that extends around at least part of the LCD display. A light guide is situated behind the opaque plate and is configured to be illuminated by the plurality of LEDs such that light from the light guide is visible through the at least translucent arc-shaped region of the opaque plate.

Abstract: A building control device includes a printed circuit board (PCB) assembly with a controller. A lighting assembly is operatively coupled to the PCB and is controlled by the controller. The lighting assembly includes a light guide that extends around a periphery of an interposing region. The light guide having a front face and one or more light sources optically coupled to the light guide such that light provided by the one or more light sources enters the light guide and is distributed to the front face of the light guide to provide a diffuse light output. A cover forms at least part of a front face of the building control device and includes a transparent region in registration with at least part of the front face of the light guide.

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned.

Abstract: Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.

Abstract: Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.

Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.

Abstract: A package comprising a first metallization portion, a first integrated device, an interconnection die, a second metallization portion, and an encapsulation layer. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The first integrated device is coupled to the first metallization portion. The interconnection die is coupled to the first metallization portion. The second metallization portion coupled to the first metallization portion through the interconnection die such that the first integrated device and the interconnection die are located between the first metallization portion and the second metallization portion. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.