Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.

Abstract: An interposer including a substantially planar substrate element with a slot formed therethrough. The slot, through which bond pads of a semiconductor die are exposed upon assembly of the interposer with the semiconductor die, includes a laterally recessed area formed in only a portion of a periphery thereof. The laterally recessed area is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad located adjacent an outer periphery of the semiconductor die and the outer periphery. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. Semiconductor device assemblies and packages that include the interposer are also disclosed, as are methods for assembling semiconductor device components with the interposer and methods for packaging such assemblies.

Abstract: Aspects of the invention provide microelectronic device assemblies including microelectronic components wire bonded to substrates, and methods of forming such assemblies. In one embodiment of the invention, a microelectronic component includes a plurality of multi-layered bond pads. Each of the multi-layered bond pads includes a bond pad base (which may comprise aluminum), an outer bond layer (which may comprise gold), and an intermediate layer between the bond pad base and the outer bond layer. This microelectronic component may be wire bonded to a substrate, with the outer bond layer and the bonding wire both comprising the same metal (e.g., gold). The bonding wire may be reliably stitch bonded to the outer bond layer of the multi-layered bond pads, facilitating manufacture of low profile microelectronic device assemblies.

Abstract: Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an embodiment, wire bonds connects pads on the die to pads on the substrate. The substrate pads are closely adjacent the die due to the die support being positioned inwardly of the peripheral surface of the die. In an embodiment, the die support includes a paste that flows outwardly when connecting the die to the substrate. The outward paste flow extends from beneath the die support but does not extend outwardly of the die so as to not interfere or contact the substrate pads.

Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: Aspects of the invention provide microelectronic device assemblies including microelectronic components wire bonded to substrates, and methods of forming such assemblies. In one embodiment of the invention, a microelectronic component includes a plurality of multi-layered bond pads. Each of the multi-layered bond pads includes a bond pad base (which may comprise aluminum), an outer bond layer (which may comprise gold), and an intermediate layer between the bond pad base and the outer bond layer. This microelectronic component may be wire bonded to a substrate, with the outer bond layer and the bonding wire both comprising the same metal (e.g., gold). The bonding wire may be reliably stitch bonded to the outer bond layer of the multi-layered bond pads, facilitating manufacture of low profile microelectronic device assemblies.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die are coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and a portion of at least a portion of the lead frame are encapsulated in an insulative material leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an embodiment, wire bonds connects pads on the die to pads on the substrate. The substrate pads are closely adjacent the die due to the die support being positioned inwardly of the peripheral surface of the die. In an embodiment, the die support includes a paste that flows outwardly when connecting the die to the substrate. The outward paste flow extends from beneath the die support but does not extend outwardly of the die so as to not interfere or contact the substrate pads.

Abstract: Aspects of the invention provide microelectronic device assemblies including microelectronic components wire bonded to substrates, and methods of forming such assemblies. In one embodiment of the invention, a microelectronic component includes a plurality of multi-layered bond pads. Each of the multi-layered bond pads includes a bond pad base (which may comprise aluminum), an outer bond layer (which may comprise gold), and an intermediate layer between the bond pad base and the outer bond layer. This microelectronic component may be wire bonded to a substrate, with the outer bond layer and the bonding wire both comprising the same metal (e.g., gold). The bonding wire may be reliably stitch bonded to the outer bond layer of the multi-layered bond pads, facilitating manufacture of low profile microelectronic device assemblies.