Patents by Inventor Limin Wang

Limin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12231654
    Abstract: A method, apparatus, and computer program product provide for management of history-based motion vector prediction (HMVP) processes for Gradual Decoding Refresh (GDR) pictures, as well as efficient implementations of mode selection within a GDR period and tuning of coding tools such as in-loop filters and Luma Mapping with Chroma Scaling (LMCS) such that current coding units within a clean area avoid use of coding information within a dirty area of a picture. In the context of a method, the method accesses a current coding unit of a picture. The method also accesses information associated with coding unit references each associated with a respective inter-coded coding unit. The method also determines at least one candidate coding unit reference based at least upon a comparison of an associated index value to a dirty index, and assigns at least one coding unit to a candidate list for selection in a coding process.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 18, 2025
    Assignee: Nokia Technologies Oy
    Inventors: Seungwook Hong, Limin Wang, Krit Panusopone
  • Publication number: 20250056009
    Abstract: In a system performing encoding or decoding for video, given a coding tree unit with surrounding reference samples on four sides of the coding tree unit, a local prediction block for a current coding unit is built. The local prediction block is used for the encoding or decoding of the video.
    Type: Application
    Filed: November 23, 2022
    Publication date: February 13, 2025
    Inventors: Limin WANG, Seungwook HONG, Krit PANUSOPONE, Jani LAINEMA
  • Patent number: 12225237
    Abstract: A system for signaling extension functions used in decoding a sequence including a plurality of pictures, each picture processed at least in part according to a picture parameter set is disclosed. An extension presence signaling flag is read and used to determine whether flags signaling the performance of extension functions are to be read. The flags are only read if indicated by the extension presence signaling flag.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: February 11, 2025
    Assignee: ARRIS Enterprises LLC
    Inventors: Yue Yu, Limin Wang
  • Patent number: 12219149
    Abstract: A system and method of defining a plane for planar coding in JVET in which first and second lines can be defined based upon pixels in left-adjacent and top-adjacent coding units. In some embodiments, the least squares method can be employed to define the relevant lines. One point along each of the lines can then be identified and the y-intercepts of the two lines can be averaged to obtain a third point. The three points can then be used to identify and define a plane for planar coding in JVET.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: February 4, 2025
    Assignee: ARRIS Enterprises LLC
    Inventors: Seungwook Hong, Limin Wang, Krit Panusopone
  • Patent number: 12200232
    Abstract: A second level intra prediction mode can be combined with one or more of sixty-seven JVET intra prediction modes during encoding of a coding unit in a video bitstream. Embodiments include making a position dependent intra prediction combination (PDPC) mode available as the second level intra prediction mode. In embodiments, when a PDPC (position dependent intra prediction combination) mode is enabled, the second level intra prediction is combined with one of the 67 selected intra predictor modes. In embodiments, the PDPC mode is only enabled or available for a predetermined subset of intra prediction modes (out of 67 possible modes), in order to reduce encoder complexity and potentially improve coding efficiency. The PDPC mode may be identifies as enabled or available by a list of modes or signaling in the video bitstream.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: January 14, 2025
    Assignee: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Seungwook Hong, Limin Wang
  • Publication number: 20250016317
    Abstract: A method of partitioning in video coding for JVET, comprising representing a JVET coding tree unit as a root node in a quadtree plus binary tree (QTBT) structure that can have quadtree or binary partitioning of the root node and quadtree or binary trees branching from each of the leaf nodes. The partitioning at any depth can use asymmetric binary partitioning to split a node represented by a leaf node into two child nodes of unequal size, representing the two child nodes as leaf nodes in a binary tree branching from the parent leaf node and coding the child nodes represented by final leaf nodes of the binary tree with JVET, wherein further partitioning of child nodes split from leaf nodes via asymmetric binary partitioning is allowed recursively along the same branch in any order with symmetric partitioning.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 9, 2025
    Applicant: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Seungwook Hong, Limin Wang
  • Patent number: 12192443
    Abstract: A method, apparatus, and computer program product provide for solving merge candidate list mismatches. In the context of a method, the method accesses a current coding unit of a picture. The method can also generate a merge candidate list comprising a plurality of coding unit representations in a predefined order. The method also determines whether a particular coding unit representation within the merge candidate list is representative of a coding unit within a dirty area of the picture and prevents the particular coding unit representation and one or more coding unit representations following the particular coding unit in the predefined order from being selected as a merge candidate for the current coding unit.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: January 7, 2025
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Limin Wang, Seungwook Hong, Krit Panusopone
  • Publication number: 20240428718
    Abstract: The present application relates to a display compensation method, including: performing an image identification process to display data to be compensated to obtain a display feature message; processing the display data to be compensated to obtain a display panel load coefficient; processing the display panel load coefficient and the display feature message to obtain a voltage drop compensation coefficient; and performing a compensation process to the display data to be compensated by the voltage drop compensation coefficient to obtain compensated display data to achieve compensation of display uniformity.
    Type: Application
    Filed: January 11, 2022
    Publication date: December 26, 2024
    Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Limin WANG
  • Publication number: 20240430476
    Abstract: Particular embodiments provide a variable, BitDepth, that may be set at a value based on a number of bits used to represent pixels in pictures of a video. The variable may be used in syntax elements in HEVC, such as the HEVC range extension, but other coding standards may be used. By using the variable, different resolutions for the video may be accommodated during the encoding and decoding process. For example, the number of pixels in the pictures may be represented by 8 bits, 10 bits, 12 bits, or another number of bits depending on the resolution. Using the BitDepth variable in the syntax provides flexibility in the motion estimation and motion compensation process. For example, syntax elements used in the weighted prediction process may take into account different numbers of bits used to represent the pictures.
    Type: Application
    Filed: July 23, 2024
    Publication date: December 26, 2024
    Applicant: ARRIS Enterprises LLC
    Inventors: Yue Yu, Limin Wang
  • Patent number: 12175918
    Abstract: A timing controller includes: an image input module configured to output respective raw data according to accessed video source data; a data processing module configured to buffer the raw data in one row and splice each row of raw data into display time control data and display luminous control data; a grayscale mapping and dividing module configured to establish a mapping relationship between the display luminous control data and a high grayscale and a mapping relationship between the display time control data and a low grayscale, to output display data; and a timing control module configured to control writing of the display data.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: December 24, 2024
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Dexing Luo, Limin Wang
  • Publication number: 20240414365
    Abstract: A method of decoding JVET video includes receiving a bitstream and calculating a final planar prediction in planar mode to predict pixel values for a current coding block. The final planar prediction may rely on using unequal weights applied to each of a horizontal and vertical predictor, where such predictors may be generated by interpolating neighboring pixels for each predicted pixel within a coding block. The computation may be made more accurate by deriving a value for a bottom right neighboring pixel.
    Type: Application
    Filed: August 21, 2024
    Publication date: December 12, 2024
    Applicant: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Yue Yu, Seungwook Hong, Limin Wang
  • Patent number: 12160591
    Abstract: A method, apparatus and a non-transitory computer readable medium are provided for receiving an input picture divided into a plurality of coding units (CUs) and comprising a virtual boundaries between a dirty area and a clean area of the input picture, each CU located within either the clean area or the dirty area. The virtual boundary is treated as a picture boundary for coding units within the clean area and as a non-boundary for coding units within the dirty area. For a current CU, a history-based motion vector prediction (HMVP) table can be prepared that identifies other CUs as HMVP candidates for inter prediction, the HMVP candidates being adjacent the current CU. The HMVP candidate CUs are limited to CUs previously coded in the clean area. The current CU can be intra coded based at least upon the HMVP candidates from the HMVP table.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 3, 2024
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Limin Wang, Krit Panusopone, Seungwook Hong
  • Publication number: 20240397304
    Abstract: This application discloses a dialing method and apparatus, and an electronic device. The dialing method includes: receiving, when a target device is connected to an electronic device, dialing request information sent by the target device, where the dialing request information is used for requesting the electronic device to dial; determining a first subscriber identity module card in the electronic device based on a historically successful call card selection status of the electronic device; and using the first subscriber identity module card to dial.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Xu LIU, Limin WANG
  • Publication number: 20240373045
    Abstract: A method, apparatus, article of manufacture, and a memory structure for signaling extension functions used in decoding a sequence comprising a plurality of pictures, each picture processed at least in part according to a picture parameter set is disclosed. In one embodiment, the method comprises reading a first extension flag signaling a first extension function in the processing of the sequence and determining if the first extension flag has a first value. Further, the method reads a second extension flag signaling a second extension function in the processing of the sequence and performs the second extension function according to the read second extension flag only if the first extension flag has a first value.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: ARRIS Enterprises LLC
    Inventors: Yue YU, Limin WANG
  • Publication number: 20240357178
    Abstract: A method of partitioning a video coding block for JVET, comprising representing a JVET coding tree unit as a root node in a quadtree plus binary tree (QTBT) structure that can have a quadtree branching from the root node and binary trees branching from each of the quadtree's leaf nodes using asymmetric binary partitioning to split a coding unit represented by a quadtree leaf node into two child coding units of unequal size, representing the two child coding units as leaf nodes in a binary tree branching from the quadtree leaf node and coding the child coding units represented by leaf nodes of the binary tree with JVET, wherein further partitioning of child coding units split from quadtree leaf nodes via asymmetric binary partitioning is disallowed.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Limin Wang
  • Publication number: 20240340416
    Abstract: A method of partitioning in video coding for JVET, comprising representing a JVET coding tree unit as a root node in a quadtree plus binary tree (QTBT structure that can have quadtree or binary partitioning of the root node and quadtree or binary trees branching from each of the leaf nodes. The partitioning at any depth can use asymmetric binary partitioning to split a child node represented by a leaf node into two child coding units of unequal size, representing the two child coding units as leaf nodes in a binary tree branching from the parent leaf node and coding the child coding units represented by final leaf nodes of the binary tree with JVET. Disclosed is a generalized method of partitioning a block, either square or rectangular, which leads to more flexible block sizes with possible higher coding efficiency.
    Type: Application
    Filed: April 5, 2024
    Publication date: October 10, 2024
    Applicant: ARRIS Enterprises LLC
    Inventors: Seungwook Hong, Krit Panusopone, Limin Wang, Yue Yu
  • Patent number: 12101500
    Abstract: A method of decoding JVET video includes receiving a bitstream and calculating a final planar prediction in planar mode to predict pixel values for a current coding block. The final planar prediction may rely on using unequal weights applied to each of a horizontal and vertical predictor, where such predictors may be generated by interpolating neighboring pixels for each predicted pixel within a coding block. The computation may be made more accurate by deriving a value for a bottom right neighboring pixel.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: September 24, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Yue Yu, Seungwook Hong, Limin Wang
  • Patent number: 12075071
    Abstract: A method, apparatus, article of manufacture, and a memory structure for signaling extension functions used in decoding a sequence comprising a plurality of pictures, each picture processed at least in part according to a picture parameter set is disclosed. In one embodiment, the method comprises reading a first extension flag signaling a first extension function in the processing of the sequence and determining if the first extension flag has a first value. Further, the method reads a second extension flag signaling a second extension function in the processing of the sequence and performs the second extension function according to the read second extension flag only if the first extension flag has a first value.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 27, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Yue Yu, Limin Wang
  • Patent number: 12069261
    Abstract: A method of partitioning in video coding for JVET, comprising representing a JVET coding tree unit as a root node in a quadtree plus binary tree (QTBT) structure that can have quadtree or binary partitioning of the root node and quadtree or binary trees branching from each of the leaf nodes. The partitioning at any depth can use asymmetric binary partitioning to split a node represented by a leaf node into two child nodes of unequal size, representing the two child nodes as leaf nodes in a binary tree branching from the parent leaf node and coding the child nodes represented by final leaf nodes of the binary tree with JVET, wherein further partitioning of child nodes split from leaf nodes via asymmetric binary partitioning is allowed recursively along the same branch in any order with symmetric partitioning.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: August 20, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Seungwook Hong, Limin Wang
  • Patent number: RE50091
    Abstract: An improved method for temporal motion vector prediction for inter block HEVC is provided that relies on a block translational model. The method adds an offset to a temporal motion vector predictor (TMVP) to improve prediction accuracy. The method first designates a current prediction block as an area for motion compensation where all the pixels inside the prediction block perform identical translation temporally using motion vectors MVs. A coordinate offset is then derived for a current prediction block from the MVs of its spatially neighboring blocks. The offset TMVP is then defined for the current prediction block as the MV of an offset block which is in the geometrical location of the current prediction block coordinate plus the coordinate offset in a specified temporal reference picture. The offset TMVP is then used to code MVs.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: August 20, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Krit Panusopone, Seungwook Hong, Limin Wang