Abstract: The present disclosure relates to methods for implementing low-power-consumption operation of a Bluetooth device and related apparatuses. In one example method, after a first electronic device establishes a first Bluetooth connection to a second electronic device, the first electronic device may disconnect the first Bluetooth connection when a first condition is met. After the first Bluetooth connection is disconnected, the first electronic device may periodically send a second broadcast packet to the second electronic device, to implement device keepalive. The second broadcast packet carries a first interval value, and the first interval value indicates an interval for sending the second broadcast packet by the first electronic device.

Abstract: Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector that is disposed on a substrate and that includes a light-absorbing layer. The light-absorbing layer includes a sidewall and a notch in the sidewall. The structure further comprises a waveguide core including a section adjacent to the notch in the sidewall of the light-absorbing layer.

Abstract: Vaporizer devices are disclosed. In one exemplary embodiment, a vaporizer device can include a vaporizer body including a first airflow path extending at least partially therethrough, and a sensor assembly residing at least partially within the vaporizer body. The sensor assembly includes a flexible sensor that is in communication with the first airflow path. The flexible sensor is configured to reversibly deflect from an initial state to a first state in response to a first user-activated force representing air being drawn through the first airflow path, and configured to reversibly deflect from the initial state to a second state in response to a second user-activated force representing an acceleration of the vaporizer body. Sensor assemblies for a vaporizer device are also provided.

Abstract: A battery case for a light-fixture includes a case body and a holder. The case body is provided with a sliding slot and a locking slot, the sliding slot communicates with an outer side of the case body, the holder includes a body portion, a locking portion and a drawer, the locking portion and the drawer are respectively connected to the body portion, and the body portion is slidably mounted on the sliding slot and is used for mounting a battery; when the body portion is completely slid into the sliding slot, the locking portion is snapped into the locking slot; the locking portion is flipped to be disengaged from the locking slot and operate the drawer, so that the body portion is slid out of the sliding slot; the design of flipping the locking portion provides an intuitive operation mode for a user.

Abstract: A battery cell includes a housing, an electric terminal disposed on the housing, and an electrode assembly accommodated in the housing. The electrode assembly includes a main body portion and a tab extending out of an end face of the main body portion and including a first connecting portion configured to be connected to the electrode terminal and a second connecting portion configured to be connected to the main body portion. Along a length direction of the end face, at least part of the first connecting portion exceeds the second connecting portion. As the first connecting portion exceeds the second connecting portion in the length direction of the end face, the connectable range of the first connecting portion in the length direction of the end face can be expanded, facilitating direct connection of the first connecting portion with the electrode terminal.

Abstract: Present invention teaches the method of using a keratin hydrolysis peptide (“KHP”) solution to enhance the drought tolerance attribute of wheat plants. By selectively choosing specific weights of feathers and water, and treating the mixture to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then infused to the soil in which the wheat seeds are planted; the solution can also be sprayed to the leaf surface of young wheat plants. Optionally, the KHP solution can be diluted by water, as disclosed in the specification, for applying to the soil around the wheat plants and for spraying to leaf surface of young wheat plants.

Abstract: This disclosure provides methods, components, devices and systems for modulation of extended long range wireless packets. Some aspects more specifically relate to communicating packets in an extended long range (ELR) communication mode. A wireless communication device may receive an indication to transmit a single-user wireless packet associated with the ELR communication mode, where the single-user wireless packet includes a preamble portion and a data portion. At least the data portion may be associated with a duplication scheme pertaining to the ELR communication mode. The wireless communication device may transmit, in accordance with the indication, the single-user wireless packet using a first quantity of duplications of at least the data portion in accordance with the duplication scheme, where the first quantity of duplications is associated with the ELR communication mode.

Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.

Abstract: Aspects of this technical solution can include a first Bandwidth Part (BWP configuration used for receiving the multicast reception in the RRC-inactive state, for receiving the multicast data channel in the RRC-inactive state, a first search space, a first control resource set, a first frequency domain location, and a first bandwidth, for receiving the multicast control channel reception in the RRC-inactive state, a second search space, a second control resource set, a second frequency domain location, and a second bandwidth, and receiving, by the wireless communication device from the network, the multicast reception according to the first configuration.

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords; and applies the first read voltage to a set of memory cells storing the one or more codewords.

Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

Abstract: A driving circuit includes a driving transistor, first to third capacitors and first to second switching transistors. The driving transistor is electrically connected between a first driving voltage terminal and a second driving voltage terminal, configured to control a driving current flowing through a light emitting element. The first switching transistor and the first capacitor are connected in series between a first terminal and a gate terminal of the driving transistor. A first terminal of the second capacitor is electrically connected to a gate terminal of the first switching transistor. The second switching transistor is electrically connected between a second terminal of the second capacitor and a first reference voltage terminal. The third capacitor is electrically connected between a gate terminal of the second switch transistor and a sweep signal line.

Abstract: A display driving device includes an emission circuit and a positive feedback circuit. The emission circuit is coupled to a first node. The emission circuit emits light according to a forward signal, a reverse signal, and a voltage level of the first node. The forward signal and the reverse signal are inversed phase of each other. The positive feedback circuit discharges the first node according to sweep signal.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A chip resistor includes a substrate, first to fourth electrodes, a resistance layer, a resin electrode layer, first and second insulating protective layers, and first and second external electrode layers. The first and second electrodes are respectively disposed on two opposite edge areas of a front surface of the substrate. The resistance layer extends from the first electrode to the second electrode. The first insulating protective layer completely covers the resistance layer. The resin electrode layer includes first to third portions respectively covering the first and second electrodes, and a portion of the first insulating protective layer. The second insulating protective layer completely covers the third portion and partially covers the first and second portions. The third and fourth electrodes are disposed on a back surface of the substrate. The first and second external electrode layers respectively connect the first and third electrodes, and the second and fourth electrodes.

Abstract: The present disclosure provides a detection circuit, an information processing apparatus, a process cartridge and a detection method. The detection circuit includes a detection unit, configured to output a first parameter related to the process cartridge; an information feedback unit, configured to be electrically connected to the detection unit and provide the image-forming apparatus with feedback information according to a connection state between the detection unit and the information feedback unit; and a control unit, configured to control the connection state between the detection unit and the information feedback unit to switch between the first state and the second state according to switching information outputted by the image-forming apparatus. In the first state, the feedback information is related to the first parameter, and the image-forming apparatus is capable of obtaining the first parameter; and in the second state, the feedback information is not related to the first parameter.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: A system and method of detecting presence of arrythmia in an electrocardiogram (ECG) signal. The method comprises steps of applying a decomposition algorithm to one or more portions of the ECG signal, each portion corresponding to at least one heartbeat. The method also comprises, for each portion, selecting at least one output of the decomposition algorithm; providing the selected at least one output to a first trained convolutional neural network (CNN) arrangement, the first CNN arrangement generating coefficients of a predetermined size; and inputting the coefficients of the predetermined size to a second trained CNN arrangement, the second CNN arrangement trained to output a classification of whether arrythmia is present in the portion of the ECG.