Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, an inner spacer layer sandwiched between the source/drain feature and the gate stack and between the first nanostructure and the second nanostructure, a semiconductor feature at a corner between the inner spacer layer and the first nanostructure, and a first passivation layer sandwiched between a first surface of the semiconductor feature and the gate stack.

Abstract: In some implementations, a thermal management system includes a heat source and a heat pipe connected to the heat source and configured to transfer thermal energy from the heat source to a plurality of condensers, each of the plurality of condensers branching off from a main pipe of the heat pipe. The heat pipe can be a variable conductance heat pipe containing a working fluid vapor. Each condenser contains a reservoir of non-condensable gas (NCG). At least one of the condensers can be controlled by heating/cooling the respective reservoir of NCG, by reservoir volume changing via bellows, and/or by NCG amount changing via NCG insertion/extraction.

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

Abstract: Methods of identifying a hot spot from a design layout or of predicting whether a pattern in a design layout is defective, using a machine learning model. An example method disclosed herein includes obtaining sets of one or more characteristics of performance of hot spots, respectively, under a plurality of process conditions, respectively, in a device manufacturing process; determining, for each of the process conditions, for each of the hot spots, based on the one or more characteristics under that process condition, whether that hot spot is defective; obtaining a characteristic of each of the process conditions; obtaining a characteristic of each of the hot spots; and training a machine learning model using a training set including the characteristic of one of the process conditions, the characteristic of one of the hot spots, and whether that hot spot is defective under that process condition.

Abstract: An instant membrane includes a base layer and a microneedle layer. The base layer has a surface. The microneedle layer is disposed on the surface of the base layer and has a plurality of microneedles. The materials of the base layer and the microneedle layer include: 9 wt %-50 wt % polyvinylpyrrolidone K30, 40 wt %-90 wt % polyvinylpyrrolidone K90 and 0.09 wt %-9 wt % mini-hyaluronic acid.

Abstract: A superabsorbent polymer and a method of fabricating the same are provided. The method includes performing a free radical polymerization reaction to a superabsorbent polymer component, so as to obtain a colloid gel. The colloid gel is cut by using a pulverizer to obtain superabsorbent polymer particles. The pulverizer has a perforated plate with changeable hole diameters, which has a first diameter of an inlet hole greater than a second diameter of an outlet hole. The method further includes performing a surface cross-linking reaction to the superabsorbent polymer particles, so as to obtain the superabsorbent polymer. Therefore, a bulk density, an absorption rate and a liquid permeability of the obtained superabsorbent polymer can be increased.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A mask according to an embodiment comprises: a first substrate; a first wiring arranged on the first substrate; a plurality of piezoelectric elements arranged on the first wiring; a second wiring arranged on the piezoelectric elements; a second substrate arranged on the second wiring; a third wiring arranged on the first substrate and electrically insulated from the first wiring; and a plurality of light-emitting elements arranged between the first and second substrates and arranged on the third wiring, wherein the plurality of light-emitting elements are arranged in areas overlapping, in a vertical direction, areas between the piezoelectric elements.

Abstract: Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

Abstract: A stylus control circuit used to control a stylus includes a positioning signal generator. The positioning signal generator is used to generate a first positioning signal having a first frequency and transmit the first positioning signal to the stylus through a first positioning transmission electrode. Wherein, the first frequency corresponds to a position of the first positioning transmission electrode, and the first positioning signal is a frequency signal without carrying any digital data.

Abstract: A training method of a generator network model and an electronic device for execution thereof are provided. The training method includes: extracting a first tensor matrix and a second tensor matrix, wherein the first tensor matrix and the second tensor matrix respectively represent a first picture and a second picture and individually include a plurality of first parameters and a plurality of second parameters; generating a plurality of third pictures according to a plurality of difference values between the first parameters of the first tensor matrix and the second parameters of the second tensor matrix; performing a similarity test on a plurality of original pictures and the plurality of third pictures; and adopting at least one of the third pictures whose similarity is lower than or equal to a similarity threshold as at least one new sample picture.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.

Abstract: A loading calculation module includes a storage unit, an inertial sensing unit and a calculation unit. The first storage unit is configured to store a relationship between an engine performance and a load, a sprung mass, a centroid distance between a sprung centroid, a rotation center and a moment of inertia. The inertial sensing unit is configured to detect a tilt angle, a tilt angular velocity, a tilt angular acceleration and a lateral acceleration. The calculation unit is configured to obtain a load corresponding to the engine performance according to the relationship between the engine performance and the load; and obtain a load position according to the moment of inertia, the tilt angle, the tilt angular velocity, the tilt angular acceleration, the lateral acceleration, the load and the centroid distance.

Abstract: An adjustment system for an article of footwear includes a body attached to an outer surface of the article of footwear and including a plurality of segments cooperating to define a chamber, the body movable between an elongated state and a collapsed state and a bladder attached to the article of footwear and defining an interior void in fluid communication with the chamber, the bladder movable from a relaxed state to a constricted state when the body is moved from the collapsed state to the elongated state.

Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.

Abstract: A system and method for enabling fine-grained access to enterprise applications in an enterprise network. The method includes receiving, via a discovery application running on a computing device, user input from a user, where the user input identifies at least one of an application name, a server name, or an Internet Protocol (IP) address associated with a computing resource for accessing an enterprise application; comparing, via the discovery application, the user input to application information stored in a database accessible by the discovery application; sending, via the discovery application, a message to the user in response to determining a match between the user input and the application information, where the message identifies a membership group containing the computing resource for accessing the enterprise application; and enabling the user to access the membership group using the computing resource when the user is a member of the membership group.

Abstract: A method includes a number of operations. A plurality of isolation regions is formed between a plurality of fin structures over a substrate. A dummy gate structure is formed over the fin structures and the isolation regions. After forming the dummy gate structure, a first refilled isolation material is formed over the isolation regions. The first refilled isolation material is etched to form a plurality of first isolation layers having a top surface below top surfaces of the fin structures. A plurality of source/drain epitaxial structures is formed in the fin structures. The dummy gate structure is replaced with a gate structure.

Abstract: An article of footwear, the article having a sole structure; and an upper coupled to a top of the sole structure. The upper includes an opening and a closure system, wherein the closure system has one or more flexible bands and one or more gripping mats attached to the one or more flexible bands. The one or more gripping mats include a plurality of microlocks, an inner film and an outer film, with the one or more flexible bands and the one or more gripping mats enclosed between the outer film and the inner film, and a first set of foam elements located on top surfaces of the one or more flexible bands and the one or more gripping mats.