Patents by Inventor Lin Lee

Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151307
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Chao-Ching CHENG, Wei-Sheng YUN, Shao-Ming YU, Tsung-Lin LEE, Chih-Chieh YEH
  • Patent number: 12287526
    Abstract: An optical element driving mechanism is provided in the present disclosure, including a first movable portion, a fixed portion, a first driving assembly and a first supporting assembly. The first movable portion is connected to a first optical element. The first movable portion is movable relative to the fixed portion. The first driving assembly drives the first movable portion to move relative to the fixed portion in a first dimension. The first supporting assembly is disposed between the first movable portion and the fixed portion. The first movable portion moves relative to the fixed portion via the first supporting assembly.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 29, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chen-Hsien Fan, Yueh-Lin Lee
  • Patent number: 12289900
    Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: April 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20250129205
    Abstract: Disclosed are a polymer including a first repeating unit represented by Chemical Formula 1 and a second repeating unit represented by Chemical Formula 2, a thin film transistor including the same, and an electronic device. In Chemical Formula 1 or 2, D1, A1, A2, L1 to L6, R1, and R2 are the same as described in the detailed description.
    Type: Application
    Filed: April 12, 2024
    Publication date: April 24, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyung Jun KIM, Jiyoung JUNG, Hyunbum KANG, Gae Hwang LEE, Bang Lin LEE
  • Publication number: 20250123535
    Abstract: An optical path control member according to an embodiment includes a first substrate; a first electrode disposed on the first substrate; a second substrate disposed on the first substrate; a second electrode disposed under the second substrate; and a light conversion part disposed between the first electrode and the second electrode and including a receiving part in which a light conversion material is disposed, wherein at least one of the first electrode and the second electrode includes a plurality of pattern electrodes, wherein the pattern electrodes extend in a direction different from a longitudinal direction of the receiving part, wherein the pattern electrodes are disposed to be spaced apart from each other between a first end and a second end of the receiving part in the longitudinal direction, wherein the pattern electrode includes a first pattern electrode disposed adjacent to the first end and a second pattern electrode disposed farther from the first end than the first pattern electrode, and where
    Type: Application
    Filed: January 2, 2023
    Publication date: April 17, 2025
    Inventors: Gyu Lin LEE, Byung Sook KIM, Seung Jin KIM
  • Publication number: 20250120158
    Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Jung CHEN, Chun-Ming LIN, Tsung-Lin LEE, Shiuan-Jeng LIN, Hung-Lin CHEN
  • Patent number: 12266723
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Grant
    Filed: March 6, 2024
    Date of Patent: April 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Patent number: 12255230
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Choh-Fei Yeap, Da-Wen Lin, Chih-Chieh Yeh
  • Patent number: 12245664
    Abstract: An article of footwear, the article including a sole structure and an upper coupled to a top of the sole structure. The upper including an opening and a closure system, wherein the closure system includes at least one first sheet and a plurality of second sheets. The at least one first sheet and the plurality of second sheets being interleaved.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: March 11, 2025
    Assignee: NIKE, Inc.
    Inventor: Yen Lin Lee
  • Publication number: 20250067954
    Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion used for connecting an optical element, a fixed portion, a first driving assembly used for driving the first movable portion to rotate relative to the fixed portion, and a guiding assembly having a first intermediate element. The first movable portion is movable relative to the fixed portion. The guiding assembly is used for applying a first stabilized force to the first movable portion for making the first intermediate element be in contact with the first movable portion or the fixed portion. The first movable portion is rotatable relative to the fixed portion.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Chih-Wei WENG, Chao-Chang HU, Yueh-Lin LEE, Chen-Hsien FAN, Chien-Yu KAO, Chia-Ching HSU, Sung-Mao TSAI, Sin-Jhong SONG
  • Patent number: 12237949
    Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: February 25, 2025
    Assignee: MEDIATEK INC.
    Inventors: Chung-Hsien Tsai, Che-Yu Chiang, Yu-Ting Liu, Tsung-Lin Lee, Chia-Sheng Peng, Ting-Ming Yang
  • Publication number: 20250063791
    Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 20, 2025
    Inventors: Tsung-Lin Lee, Wei-Yang Lee, Ming-Chang Wen, Chien-Tai Chan, Chih Chieh Yeh, Da-Wen Lin
  • Patent number: 12230634
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Shuan Li, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 12229945
    Abstract: A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: February 18, 2025
    Assignee: PDF Solutions, Inc.
    Inventors: Tomonori Honda, Lin Lee Cheong, Richard Burch, Qing Zhu, Jeffrey Drue David, Michael Keleher
  • Patent number: 12211910
    Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Jung Chen, Chun-Ming Lin, Tsung-Lin Lee, Shiuan-Jeng Lin, Hung-Lin Chen
  • Patent number: 12211644
    Abstract: An optical system is provided, including a housing, an optical element, a first movable part, a driving assembly, and a temperature adjusting module. The optical element is disposed on the housing. The first movable part is movably connected to the housing. The driving assembly is configured to drive the first movable part to move relative to the housing. The temperature adjusting module is disposed in the housing for adjusting the temperature of the optical system.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: January 28, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Hsi Wang, Chao-Chang Hu, Yueh-Lin Lee, Che-Wei Chang
  • Patent number: 12202836
    Abstract: Compounds, tautomers and pharmaceutically acceptable salts of the compounds are disclosed, wherein the compounds have the structure of Formula Ia, as defined in the specification. In an embodiment, a pharmaceutical composition can be in a liquid dosage form and can comprise a therapeutically effective amount of the compound or a pharmaceutically acceptable salt thereof as an adjuvant and a therapeutic agent. In another embodiment, a method of adjuvant treating a disorder or condition can comprising administering the pharmaceutical composition to a patient.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: January 21, 2025
    Assignee: Pfizer Inc.
    Inventors: John David Trzupek, Katherine Lin Lee, Mark Edward Bunnage, Seungil Han, David Hepworth, Frank Eldridge Lovering, John Paul Mathias, Nikolaos Papaioannou, Betsy Susan Pierce, Joseph Walter Strohbach, Stephen Wayne Wright, Christoph Wolfgang Zapf, Lori Krim Gavrin, Arthur Lee, David Randolph Anderson, Kevin Joseph Curran, Christoph Martin Dehnhardt, Eddine Saiah, Joel Adam Goldberg, Xiaolun Wang, Horng-Chih Huang, Richard Vargas, Michael Dennis Lowe, Akshay Patny
  • Patent number: 12199169
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Publication number: 20250013636
    Abstract: An NLQ-SQLQ tool or service of a provider network may receive a natural language query (NLQ) from a client and convert the NLQ to an SQL query using ontological codes and placeholders. For one or more portions of the NLQ, the tool/service determines that the portion is associated with one or more codes of an ontology. The tool/service then assigns, based on criteria, a particular code to the portion. The tool/service replaces portions of the NLQ with different argument placeholders to generate a modified NLQ. A trained model converts the modified NLQ into an initial SQL query that has argument placeholders and subquery placeholders. The tool/service generates a final SQL query based on the initial SQL query, predefined SQL subquery templates associated with the subquery placeholders, and codes associated with the argument placeholders. The tool/service executes the final SQL query and sends results to the client.
    Type: Application
    Filed: September 20, 2024
    Publication date: January 9, 2025
    Applicant: Amazon Technologies, Inc.
    Inventors: Miguel Romero Calvo, Tesfagabir Meharizghi, Thiruvarul Selvan Senthivel, Saman Sarraf, Lin Lee Cheong
  • Patent number: 12185456
    Abstract: A circuit board and an electronic package using the same are provided. The circuit board includes a rigid board body, at least one bendable extension portion, connecting members, and shielding members. The rigid board body includes conductive layers and dielectric layers therebetween. The extension portion is connected to a side of the rigid board body and formed by layers of the conductive layers and at least one layer of the dielectric layers extending outside the rigid board body. The connecting members are arranged on a connecting end of the extension portion and electrically connected to a signal layer of the conductive layers. The shielding members are arranged around the corresponding connecting members and electrically connected to a ground layer of the conductive layers. The connecting members and the shielding members protrude from the connecting end. A height of the shielding members is lower than a height of the connecting members.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: December 31, 2024
    Assignees: First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd., Industrial Technology Research Institute
    Inventors: Min-Lin Lee, Sheng-Che Hung, Ching-Shan Chang, Ying-Tsuen Liou