Abstract: The invention provides a high thermal conductivity fluororesin composition and products thereof. The high thermal conductivity fluororesin composition includes a polytetrafluoroethylene resin, a fluorine-containing copolymer, spherical inorganic fillers and impregnation aids.

Abstract: A composite material substrate includes an inorganic filler, a resin composition, and a dispersant. The resin composition includes a bismaleimide resin, a naphthalene ring-containing epoxy resin, and a benzoxazine resin. The inorganic filler, the resin composition, and the dispersant are mixed together.

Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.

Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.

Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.

Abstract: The solar cell includes: a substrate; a tunneling dielectric layer located on the first surface of the substrate; multiple doped conductive layers, where the multiple doped conductive layers are located on a surface of the tunneling dielectric layer away from the substrate, and are disposed at intervals; multiple first electrodes, where the multiple first electrodes are disposed at intervals, extend along a first direction, are arranged on a side of the multiple doped conductive layers away from the substrate, and are electrically connected to the multiple doped conductive layers; at least one conductive transport layer, where the at least one conductive transport layer is located between every two adjacent doped conductive layers in the multiple doped conductive layers, and is in contact with a side surface of the multiple doped conductive layers.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A semiconductor processing method includes: selecting a target state of a reticle based on a given data set, wherein the given data set comprises temperature profiles of the reticle correlated to a target overlay performance, and the target state is a state in which a deformation of the reticle is substantially unchanged; regulating the reticle to reach the target state; and performing an exposure process on a target workpiece by using the reticle.

Abstract: A resin composition includes resin and inorganic filler. The resin includes liquid rubber resin, polyphenylene ether resin, and a crosslinking agent. Compared to a total of 100 parts by mass of the resin, the usage amount of the inorganic filler is at least greater than or equal to 40 parts by mass.

Abstract: A multifunctional catalyst, a method for producing the same, and a method for using the same are provided. The multifunctional catalyst is applicable for recycling a polyester fabric. The multifunctional catalyst includes a carrier, and a first functional ionic liquid and a second functional ionic liquid that are grafted on the carrier. The carrier is an inorganic composite powder material, and is composed of following chemical components: C: Na—Ni/Al2O3. In a process of recycling the polyester fabric, the multifunctional catalyst simultaneously decolorizes and depolymerizes the polyester fabric. The first functional ionic liquid is used to decolorize the polyester fabric, and the second functional ionic liquid is used to depolymerize the polyester fabric.

Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: An apparatus for transferring an electronic component including a first platform, a second platform, an actuator mechanism, and a flexible push generator is provided. The first platform is configured to carry a carrier substrate. The second platform is configured to carry a target substrate. The actuator mechanism is configured to actuate the first platform and the second platform to approach and move away from each other. The flexible push generator is disposed near the first platform or the second platform and generating a plurality of flexible pushes toward the first platform and the second platform in response to the first platform and the second platform actuated in a way that the first platform and the second platform approach each other.

Abstract: A photovoltaic cell is provided, including a substrate, a doped layer, a tunneling dielectric layer, doped conductive layers, first electrodes, and conductive transport layers. A doping concentration of the doped layer is greater than that of the substrate. The doped layer includes first doped regions, second doped regions and third doped regions. A doping concentration of each first doped region is less than that of each second doped region and that of each third doped region. The tunneling dielectric layer is disposed on the first and second doped regions. Each doped conductive layer is aligned with a first doped region and is disposed on a tunneling dielectric layer. Each first electrode is disposed on and electrically connected to the doped conductive layer. Each conductive transport layer is aligned with a second doped region and is disposed on the tunneling dielectric layer.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A powder composition includes a first powder, a second powder, and a modified functional group. A particle size range of the first powder is between 1 micron and 100 microns. The second powder and the modified functional group are modified on the first powder. A particle size range of the second powder is between 10 nanometers and 1 micron. A manufacturing method of a powder composition is also provided.

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.