Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor layer structure. Implanted dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: The present disclosure is directed to a system and method for embedding metallic glass with nanocrystals. In some implementations, a method includes positioning at least one of metallic glass or a source configured to emit a particle beam such that the metallic glass and the source are proximate. Nanocrystals embedded in the metallic glass are formed by irradiating the metallic glass with the particle beam.

Abstract: The present disclosure is directed to a system and method for operating a device including embedded nanoparticles. In some implementations, the method includes selectively illuminating at least a portion of a device including material having embedded nanoparticles. The nanoparticles emit electrons in response to light at a certain frequency or above. At least one operating parameter of the device is adjusted to direct at least a portion of the emitted electrons.

Abstract: The transfer of strained semiconductor layers from one substrate to another substrate involves depositing a multilayer structure on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the deposited multilayer structure is bonded to a second substrate and is separated away at the interface, which results in transferring a multilayer structure from one substrate to the other substrate. The multilayer structure includes at least one strained semiconductor layer and at least one strain-induced seed layer. The strain-induced seed layer can be optionally etched away after the layer transfer.

Abstract: A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Abstract: A method for transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves deposition of a doped semiconductor layer on a substrate and epitaxial growth of a thin, monocrystalline, semiconductor layer on the doped layer. After bonding the thin epitaxial monocrystalline semiconductor layer to a second substrate, hydrogen is introduced into the doped layer, and the thin layer is cleaved and transferred to the second substrate, with the cleaving controlled to happen at the doped layer.

Abstract: A method for transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.

Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: A method of forming a stable unction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.

Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.

Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.