Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.

Abstract: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

Abstract: Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.