Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.

Abstract: Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: A low-power low-voltage buffer with a half-latch is provided. The half-latch buffer design may provide increased speed without dramatically increasing power consumption.

Abstract: Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A sense amplifier circuit for a memory integrated circuit provides good performance and relatively low power consumption. The circuitry includes a cascode output and a feedback (214) from the cascode output to a transistor (M1) to provide additional pull-up current at a bit line (206).

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.