Patents by Inventor Lin Wang

Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111334
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20210108089
    Abstract: The present invention relates to a process comprising the step of contacting an aqueous dispersion of swelled polymer particles with a rheology modifier and a binder to form a coatings composition with a VOC of less than 50 g/L. The swelled polymer particles arise from neutralization of alkali swellable polymer particles having a high acid core content and a low Tg shell. The composition arising from the process of the present invention is useful for improving open time, especially for low VOC coatings applications.
    Type: Application
    Filed: February 26, 2018
    Publication date: April 15, 2021
    Inventors: James K. Bardman, Jonathan DeRocher, Andrew Hejl, Anthony K. VanDyk, Lin Wang, Kimy Yeung
  • Patent number: 10976151
    Abstract: An optical interferometer includes a beam splitter module and an optical sensor. The beam splitter module includes a lens assembly and a splitter cube. A light incident surface of the splitter cube is substantially orthogonal to an optical axis of the lens assembly. An acute angle is between the light incident surface and a light splitting surface of the splitter cube. A sampling surface of the splitter cube is substantially parallel to the light incident surface. A light reflecting surface of the splitter cube is substantially orthogonal to the light incident surface. The light incident surface is closer to the lens assembly than the sampling surface. A reference arm is defined between a splitter position on the light splitting surface and the light reflecting surface, a sample arm is defined between the splitter position and the sampling surface, and the reference arm is longer than the sample arm.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 13, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan Chin Lee, Ting Wei Chang, Chi Shen Chang, Chy Lin Wang
  • Patent number: 10978389
    Abstract: A device includes a first dielectric layer, a first conductor, a second dielectric layer, a second conductor, and an etch stop layer. The first conductor is in the first dielectric layer. The second dielectric layer is over the first dielectric layer. The second conductor is in the second dielectric layer and electrically connected to the first conductor. The second conductor has a first portion over a top surface of the first conductor and a second portion extending downwards from the first portion and around the first conductor. The etch stop layer has a first portion between the second portion of the second conductor and the first dielectric layer and a second portion between the first dielectric layer and the second dielectric layer. A top surface of the first portion of the etch stop layer is lower than a top surface of the second portion of the etch stop layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Sheng Zheng, Chih-Lin Wang
  • Patent number: 10962735
    Abstract: The invention provides an insert molded lens driving apparatus including a driving coil having two ends, wherein the lens holder includes multiple insert members for electrical connection partially embedded into the lens holder and spaced apart from each other. Each of the insert members electrically coupled to the driving coil and having a first connecting end extending along a first direction and a second connecting end extending along a second direction, which.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 30, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Hung-Lin Wang, Chen-Chi Kuo, Shou-Jen Liu, Kun-Shih Lin
  • Publication number: 20210089163
    Abstract: A touch device and an operation method thereof is provided. By determining whether the operating event of the touch device or its touchpad satisfies an exclusion condition, the command triggered when the touchpad is pressed is determined to be ignored or not. Therefore, the corresponding command triggered by pressing the touchpad downward is automatically excluded when it does not want to be triggered. Therefore, the user can naturally disable the function of the corresponding command, which is executed when the pressing module is triggered, during use without using other controls, thereby improving the convenience of use.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 25, 2021
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Hsueh-Wei YANG, Ting-Jan YANG, Sung-Lin Wang
  • Publication number: 20210082482
    Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
  • Publication number: 20210079033
    Abstract: There are provided compounds of Formula (A) and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for the prevention or treatment in a mammal of joint and bone disorders such as arthritis and osteoporosis.
    Type: Application
    Filed: December 17, 2018
    Publication date: March 18, 2021
    Inventors: Xianqi KONG, Jiasheng LU, Jiamin GU, Xiang JI, Daiqiang HU, Xiuchun ZHANG, Xinyong LV, Jinchao AI, Dongdong WU, Lin WANG, Dongqing ZHU, Xiaolin HE
  • Publication number: 20210074907
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
    Type: Application
    Filed: October 1, 2019
    Publication date: March 11, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 10943948
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Publication number: 20210066579
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Application
    Filed: September 30, 2019
    Publication date: March 4, 2021
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Publication number: 20210065750
    Abstract: A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
    Type: Application
    Filed: October 3, 2019
    Publication date: March 4, 2021
    Inventors: Po-Kai Hsu, Hung-Yueh Chen, Kun-I Chou, Jing-Yin Jhang, Hui-Lin Wang, Yu-Ping Wang
  • Patent number: 10937946
    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
  • Patent number: 10934363
    Abstract: The present application provides single-domain antibodies, and chimeric antigen receptors comprising one or more antigen binding domains each comprising a single-domain antibody. Further provided are engineered immune effector cells (such as T cells) comprising the chimeric antigen receptors. Pharmaceutical compositions, kits and methods of treating cancer are also provided.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 2, 2021
    Assignee: Legend Biotech USA Inc.
    Inventors: Xiaohu Fan, Chuan-Chu Chou, Qiuchuan Zhuang, Pingyan Wang, Lin Wang, Lei Yang, Jiaying Hao
  • Patent number: 10931177
    Abstract: A generator includes: a built-in voltage controller disposed inside the housing of the motor and connected to the stator; a loop changeover switch, wherein one side of the three groups of loop polar phase contact points is connected to the current output unit through three phase lines, and the other side is connected to the current output unit through three loop lines; a three-phase short-circuit changeover switch is in a spaced arrangement with the loop changeover switch and includes three groups of short-circuit polar phase contact points, one side of which is connected to each other through short-circuit wire, and the other side is connected to each phase line; three converted-voltage output lines, wherein one end electrically connected to the loop polar phase contact points of the loop changeover switch is connected to one side of the loop lines; the other end is used to connect to a power device.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 23, 2021
    Inventors: Yao-Lin Wang, Chong-Ying Wang
  • Patent number: 10932063
    Abstract: A vibration transducer for sensing vibrations includes a first flexible triboelectric member, a second flexible triboelectric member, a plurality of attachment points, a first electrode and a second electrode. The first flexible triboelectric member includes a first triboelectric layer and a material being on a first position on a triboelectric series. A conductive layer is deposited on the second side thereof. The second flexible triboelectric member includes a second triboelectric layer and a material being on a second position on the triboelectric series that is different from the first position on the triboelectric series. The second triboelectric member is adjacent to the first flexible triboelectric member. When the first triboelectric member comes into and out of contact with the second triboelectric member as a result of the vibrations, a triboelectric potential difference having a variable intensity corresponding to the vibrations can be sensed between the first and second triboelectric members.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 23, 2021
    Assignee: Georgia Tech Research Corporation
    Inventors: Nivedita Arora, Gregory D. Abowd, Mohit Gupta, Diego Osorio, Seyedeh Fereshteh Shahmiri, Thad Eugene Starner, Yi-Cheng Wang, Zhengjun Wang, Zhong Lin Wang, Steven L Zhang, Peter McAughan, Qiuyue Xue, Dhruva Bansal, Ryan Bahr, Emmanouil Tentzeris
  • Patent number: 10923068
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 16, 2021
    Assignee: E INK HOLDINGS INC.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Yu-Lin Wang, Po-Hsin Lin
  • Patent number: 10916694
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210036053
    Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Hung-Chan Lin, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20210035620
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Application
    Filed: August 29, 2019
    Publication date: February 4, 2021
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin