Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.

Abstract: A multi-compartment container has a main body, an upper cover, a lower cover, and a base. The base is mounted on a bottom side of the main body. The lower cover is mounted on a top of the main body. The upper cover is rotatably mounted on a top of the lower cover. The main body has multiple compartments symmetrically surrounding a central axis. The lower cover has a central board and multiple flip covers. The flip covers are disposed along edges of the central board, and a location of each one of the flip covers corresponds to a respective one of the compartments of the main body. The upper cover has a flipping notch which corresponds to one of the flip covers, thereby flipping up the flip cover. The multi-compartment container is capable of storing different medications.

Abstract: A laser welding control method, apparatus and system, and an electronic device are disclosed, the method includes: receiving a current position of a welding head fed back by an encoder; determining whether the current position reaches a set position; and in response to the welding head reaching the set position, sending a laser control signal to a laser device to control the laser device to output laser at the set position.

Abstract: The present invention provides a multifunctional pacemaker wire conversion device and an application method thereof. The device includes a box body, a permanent electrode female connector, a permanent electrode male connector, a temporary electrode female connector, a temporary electrode male connector, and a circuit line. A cavity is formed in the box body, the permanent electrode female connector, the permanent electrode male connector, the temporary electrode female connector, and the temporary electrode male connector are disposed on the box body, and the permanent electrode female connector, the permanent electrode male connector, the temporary electrode female connector, and the temporary electrode male connector are electrically connected to each other through the circuit line disposed in the cavity.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A method for forming a magnetic memory device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a bottom electrode layer, forming a dielectric cap layer on the MTJ stack, and forming a metal cap layer on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

Abstract: A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

Abstract: A semiconductor structure includes a substrate having a memory device region covered by a first dielectric layer, a memory stack structure on the first dielectric layer, an insulating layer conformally covering the memory stack structure and the first dielectric layer, a second dielectric layer on the insulating layer, an etching stop layer on the second dielectric layer, a third dielectric layer on the etching stop layer, and a second interconnecting structure through the third dielectric layer, the etching stop layer and the insulating layer to contact a top surface of the memory stack structure. The insulating layer directly contacts a bottom surface of the etching stop layer and partially covers a bottom surface and a lower sidewall of the second interconnecting structures.

Abstract: A circuit, method and device for addressing CAN nodes are provided. The circuit includes: a fuse adapter board including a short-circuited circuit; a first CMU including a first MCU and a first CAN identification circuit; and a second CMU including a second MCU and a second CAN identification circuit. The fuse adapter board is connected to the first MCU or the second MCU through the short-circuited circuit, and is configured to control the short-circuited circuit to be shorted to enable a level on a GPIO pin of the first MCU or the second MCU connected to the short-circuited circuit to be a low level, so that the first MCU and the second MCU set their respective CAN addressing based on the respective levels of the respective GPIO pins.

Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: Provided is a recombinant KOD polymerase, which is the following A) or B): the polymerase shown in A) is a protein having DNA polymerase activity that is obtained by modifying amino acid residues in at least one of the following 18 positions in a wild-type KOD DNA polymerase amino acid sequence: 675th, 385th, 710th, 674th, 735th, 736th, 606th, 709th, 347th, 349th, 590th, 676th, 389th, 589th, 680th, 384th, 496th and 383rd; the polymerase described by B) is a protein having DNA polymerase activity that is derived from A) by adding a tag sequence to an end of the amino acid sequence of the protein shown in A).

Abstract: The present invention relates to a process for synthesizing a compound of formula (I), or a pharmaceutically acceptable salt thereof, which is useful for prophylaxis and treatment of a viral disease in a patient relating to hepatitis B infection or a disease caused by hepatitis B infection.

Abstract: The Bacillus velezensis M173 was deposited with the Guangdong Microbial Culture Collection Center with a deposit number of GDMCC No. 61434. After being prepared into a seed-coating agent, Bacillus velezensis M173 can promote the growth and germination of plants and significantly improve the control effect on pathogens. Moreover, Bacillus velezensis M173 can relieve the condition of dead seedlings of crops at seedling stage after being applied to the crops. In particular, both pot experiments and field experiments prove that the Bacillus velezensis M173 of the present invention has a significant control effect on fungal and bacterial diseases, in particular, bacterial wilt and stem rot. Therefore, the Bacillus velezensis M173 of the present invention has broad application prospects.

Abstract: A comprehensive consumption control system for a plug-in hybrid electric (PHEV) vehicle includes a user interface configured to receive a user selection from a plurality of different comprehensive consumption modes for an electrified powertrain, the selected comprehensive consumption mode specifying a distributed usage of power sources for an electric motor and an engine, wherein the power source for the electric motor is state of charge (SOC) in a battery system and the power source for the engine is fuel in a fuel system and a controller in communication with the user interface and configured to receive, from the user interface, the selected comprehensive consumption mode for the electrified powertrain, and control the electrified powertrain based on the selected comprehensive consumption mode such that the electric motor and the engine use the battery system SOC and the fuel according to the distributed usage specified by the selected comprehensive consumption mode.

Abstract: There are provided compounds of Formula (A) and pharmaceutically acceptable salts and esters thereof, and pharmaceutical compositions thereof, used for the prevention or treatment in a manual of joint and bone disorders such as arthritis and osteoporosis.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: This specification provides a meta learning method of a deep learning model and a meta learning system of a deep learning model, and relates to the field of deep learning technologies. The meta learning method of a deep learning model is applied to a cluster including N processing nodes, and the method includes: obtaining a training dataset, where the training dataset includes training samples corresponding to a plurality of tasks; and performing a plurality of times of iterative training on the deep learning model based on the training dataset in parallel by using the N processing nodes in the cluster, to obtain a meta learning parameter of the deep learning model, In each time of iterative training, each of the N processing nodes learns some parameters of the deep learning model by using some training samples in the training dataset, and the some training samples correspond to a same task.

Abstract: The present application discloses a hardened multicore connector and a fiber optic connector. The hardened multicore connector is configured to detachably connect to an external fiber optic connector and comprises a main body, a buffer member, a fiber optic assembly and a housing sequentially connected, wherein the main body is detachably connected to the housing to limit an axial movement among the main body, the fiber optic assembly, the buffer member and the housing; a limiting structure is provided in the housing and is configured to engage with the fiber optic assembly to limit a circumferential rotation of the fiber optic assembly; and the main body is provided with a first abutting portion, an outer sidewall of the fiber optic assembly is provided with a second abutting portion, and two end surfaces of the buffer member respectively abut against the first abutting portion and the second abutting portion.