Patents by Inventor Lin Wang
Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830924Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.Type: GrantFiled: June 27, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang
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Patent number: 11831355Abstract: An ultrasonic data transmission method, apparatus and system, a terminal device and a medium are provided. The method is applied to a transmitting terminal which includes at least two ultrasonic signal transmitting arrays. The method includes: a single-frequency ultrasonic coding signal of to-be-transmitted information corresponding to each ultrasonic signal transmitting array is respectively determined, ultrasonic codes of to-be-transmitted information corresponding to different ultrasonic signal transmitting arrays being different; and corresponding at least two single-frequency ultrasonic code signals are transmitted through the at least two ultrasonic signal transmitting arrays to a receiving terminal in a focusing mode, frequency bands of transmitting frequencies of different ultrasonic signal transmitting arrays being different.Type: GrantFiled: March 25, 2021Date of Patent: November 28, 2023Assignee: Beijing Xiaomi Mobile Software Co., Ltd.Inventors: Runyu Shi, Yuqing Hua, Song Mei, Wei Lu, Lin Zhang, Naichao Guo, Kai Wang
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Patent number: 11831386Abstract: Embodiments of the present disclosure relate to methods, devices and computer readable media for beam failure recovery for a secondary cell. In example embodiments, a method implemented in a terminal device includes in response to a beam failure on a secondary cell (Scell), transmitting a scheduling request to a network device; receiving, from the network device and on a primary cell (Pcell), a response indicating a resource allocated to the terminal device; transmitting, to the network device and using the allocated resource, a beam failure recovery request comprising a beam index of a beam selected from available beams on the Scell by the terminal device, to recover communication between the terminal device and the network device via the selected beam on the Scell.Type: GrantFiled: August 9, 2018Date of Patent: November 28, 2023Assignee: NEC CORPORATIONInventors: Fang Yuan, Lin Liang, Gang Wang
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Patent number: 11827970Abstract: Some implementations described herein provide a shutter disc for use during a conditioning process within a processing chamber of a deposition tool. The shutter disc described herein includes a material having a wave-shaped section to reduce heat transfer to the shutter disc and to provide relief from thermal stresses. Furthermore, the shutter disc includes a deposition of a thin-film material on a backside of the shutter disc, where a diameter of the shutter disc causes a spacing between an inner edge of the thin-film material and an outer edge of a substrate support component. The spacing prevents an accumulation of material between the thin film material and the substrate support component, reduces tilting of the shutter disc due to a placement error, and reduces heat transfer to the shutter disc.Type: GrantFiled: May 5, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Wang, Chin-Szu Lee, Hua-Sheng Chiu, Yi-Chao Chang, Zih-Shou Mue
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Patent number: 11829644Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.Type: GrantFiled: January 22, 2022Date of Patent: November 28, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
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Publication number: 20230378302Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230378270Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
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Publication number: 20230371877Abstract: A method for analyzing myocardial ischemia in resting electrocardiogram comprises establishing the database, grouping in a database, determining the threshold value for the group, processing the to-be-determined resting electrocardiogram, and determining the stenosis degree of the coronary artery.Type: ApplicationFiled: July 18, 2022Publication date: November 23, 2023Inventors: Chun-Lin Wang, Chiu-Chi Wei, Pin-Hsiang Chang
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Publication number: 20230378352Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Wei HSU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Jia-Ni YU, Kuan-Lun CHENG, Chih-Hao WANG
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Publication number: 20230375616Abstract: A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Lin QI, Xiaoqiong DU, Juan WANG, Jinyu TONG
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Publication number: 20230378044Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.Type: ApplicationFiled: February 14, 2023Publication date: November 23, 2023Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chun-Ting Kuo, Yu-Hui Hu, Chih-Hao Chiang, Chen-Yu Wang, Kung-An Lin, Pai-Sheng Cheng
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Publication number: 20230380128Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.Type: ApplicationFiled: July 25, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
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Publication number: 20230378072Abstract: An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.Type: ApplicationFiled: July 5, 2022Publication date: November 23, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Shuai-Lin Liu, Nai-Hao Kao, Chao-Chiang Pu, Yi-Min Fu, Yu-Po Wang
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Publication number: 20230378305Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Li WANG, Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Tzer-Min Shen, Pinyen Lin
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Patent number: 11821964Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.Type: GrantFiled: July 13, 2020Date of Patent: November 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
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Patent number: 11821637Abstract: An energy-saving system using electric heat pump to recover flue gas waste heat for district heating uses flue gas waste heat recovery tower to absorb the sensible and latent heat in the high-temperature flue gas by direct contact heat and mass transfer. The circulating water is sprayed from the top and the flue gas flows upwards in the tower. The electric heat pump is indirectly connected with circulating water through the anti-corrosion and high-efficiency water-water plate heat exchanger. The return water of the heat-supply network enters the electric heat pump through the anti-corrosion and high-efficiency water-water plate heat exchanger and exchanges heat indirectly with the high-temperature circulating water. The electric heat pump uses the electric energy of the power plant as the driving power.Type: GrantFiled: March 25, 2019Date of Patent: November 21, 2023Assignee: DALIAN UNIVERSITY OF TECHNOLOGYInventors: Haichao Wang, Xiaozhou Wu, Ruoyu Zhang, Lin Duanmu, Xiangli Li
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Patent number: 11825664Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.Type: GrantFiled: March 24, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Tsann Lin
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Patent number: 11821729Abstract: A tight-integrated navigation method assisted by Elman neural network when GNSS signals are blocked based on the tight-integrated navigation system model of the INS and GNSS, where the dynamic Elman neural network prediction model is used to train the inertial navigation error model and the GNSS compensation model, so as to solve the problem of tight-integrated navigation when the GNSS signals are blocked. When the GNSS signals are blocked, the trained neural network is used to predict the output error of GNSS and compensate the output of inertial navigation, so that the error will not diverge sharply, and the system can continue to work in the integrated navigation mode. The low-cost tight-integrated navigation module is used, and the collected information is preprocessed to form the sample data for training the neural network to train the Elman neural network model.Type: GrantFiled: September 7, 2020Date of Patent: November 21, 2023Assignee: Harbin Engineering UniversityInventors: Lin Zhao, Zihang Peng, Jicheng Ding, Kun Wang, Yaguo Bai, Yongchao Zhang, Renlong Wang
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Publication number: 20230369326Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN
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Publication number: 20230369096Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Tai-I YANG, Wei-Chen CHU, Yung-Chih WANG, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE