Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate comprising a magnetic random access memory (MRAM) region and a logic region, forming a first magnetic tunneling junction (MTJ) on the MRAM region, forming a first inter-metal dielectric (IMD) layer around the first MTJ, and then forming a first metal interconnection extending from the MRAM region to the logic region on the first MTJ. Preferably, the first metal interconnection on the MRAM region and the first metal interconnection on the logic region have different heights.

Abstract: The disclosed techniques enable resource configuration for sidelink communications. An example method includes receiving, by a first network element, a sidelink resource request transmitted from a communication node. The method also includes communicating, via an interface between the first network element and a second network element, information about resource configuration for the communication node. The method further includes transmitting, by the first network element, a response to the sidelink resource request.

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Abstract: The present invention provides a data analytic scheme for screening biomarkers for differential diagnosis of the status of Parkinson's disease, Parkinson's disease with mild cognitive impairment, Parkinson's disease dementia, Alzheimer's disease, and/or multiple system atrophy, the methodology implementing the same and the results of the screening thereof. Biomedical Oriented Logistic Dantzig Selector (BOLD Selector) was developed to identify candidate microRNAs and extracellular vesicle proteins effective at discerning between any two of the above mentioned disease categories from profiling results. The prediction models are finalized by establishing logistic regression formula for each pair of patient group differentiation.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: Self-aligned gate isolation/cutting techniques for multigate devices are disclosed herein. An exemplary multigate device includes a first gate having a gate stack that surrounds a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate endcap is disposed on the first sidewall. A gate helmet is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate helmet. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to a second gate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first IC chip bonded to a second IC chip. The first chip IC includes a first bond structure. The first bond structure includes a first plurality of conductive bond pads and a first plurality of shield structures disposed between adjacent conductive bond pads among the first plurality of conductive bond pads. The second IC chip includes a second bond structure. A bonding interface is disposed between the first bond structure and the second bond structure. The second bond structure includes a second plurality of conductive bond pads and a second plurality of shield structures. The first plurality of conductive bond pads contacts the second plurality of conductive bond pads and the first plurality of shield structures contacts the second plurality of shield structures at the bonding interface.

Abstract: A double-sided ultrasonic rolling cooperative strengthening system and a control method thereof are provided. The system includes a first mechanical arm subsystem, a second mechanical arm subsystem, a first ultrasonic rolling strengthening subsystem, a second ultrasonic rolling strengthening subsystem and a servo turntable (13); the servo turntable (13) is configured to fix a blade to be processed; the first ultrasonic rolling strengthening subsystem is provided at an end of the first mechanical arm subsystem; and the second ultrasonic rolling strengthening subsystem is provided at an end of the second mechanical arm subsystem.

Abstract: The present disclosure provides a method for determining effective storage capacity of a gas storage reconstructed from a water-flooded volatile oil reservoir. The method includes: determining an oil reservoir water flooding recovery ratio; determining crude oil production extracted only due to a water flooding effect in an oil reservoir development process; determining an oil-bearing pore volume of a flooded zone of a reservoir influenced due to the water flooding effect and an oil-bearing pore volume of a pure oil zone of a reservoir not influenced due to the water flooding effect corresponding to its original state before an oil reservoir is put into development when the gas storage is reconstructed from the oil reservoir; determining an effective pore volume for gas storage; and computing the effective storage capacity of the gas storage reconstructed from the water-flooded volatile oil reservoir.

Abstract: The present disclosure relates to an apparatus and a method for a real-time clock (RTC) module of a system-on-chip (SoC), and provides an apparatus for powering battery-powered RTC module of an SoC. The apparatus is integrated in the RTC module and comprises: a first regulator stage comprising one or more regulators, wherein the first regulator stage is configured to provide a core power supply voltage (VDD_CORE) on the basis of battery output voltage (VDD_BAT); and a crystal oscillator I/O unit, the crystal oscillator I/O unit being powered by the core power supply voltage (VDD_CORE) and an I/O power supply voltage (VDD_IO), wherein the apparatus directly provides the battery output voltage (VDD_BAT) as the I/O power supply voltage (VDD_IO).

Abstract: An operation method of a direct memory access (DMA) circuit comprising a buffer circuit and two channels includes following steps: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of first and second channels that respectively correspond to first and second data; determining a read address according to the first start address and a read count; reading a first part of the first data from the buffer circuit according to the read address and updating the read count; reading at least one part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count; and reading a second part of the first data from the buffer circuit according to the updated read address.

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Abstract: An energy-saving preparation system for a silicon-carbon anode material of a lithium battery includes a pulverizing box and a feed port. The feed port is formed in the top of the pulverizing box; a pulverizing roller is rotatably mounted inside the pulverizing box; the inner wall of the pulverizing box is symmetrically fixedly connected with mounting plates; fixed plates are symmetrically fixedly connected between the two mounting plates; the surfaces of the two mounting plates are fixedly connected with rotating devices; the two fixed plates are fixedly connected with the rotating devices; the rotating devices are slidably connected with the pulverizing roller; the upper parts of the two mounting plates are fixedly connected with transverse plates; the rotating devices and the transverse plates are rotatably installed.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to form a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.

Abstract: The invention discloses a blockchain-based intrusion detection system for railway signal, which is built on a blockchain's distributed chain structure, without a central, trusted control center. This design mitigates the vulnerabilities associated with centralized intrusion detection centers. Additionally, by utilizing a blockchain-based distributed structure, it also eliminates the risk of a single point of failure for the intrusion detection center. Moreover, the data within the blockchain-based intrusion detection system is highly resistant to malicious tampering. This is achieved by leveraging the consensus mechanism inherent in the blockchain, which can achieve consensus among intrusion detection nodes. The current invention solves the internal evil attacks and avoid the inability to reach consensus between nodes due to internal evil, thereby affecting the intrusion detection performance; at the same time, the intrusion detection model can resist external network attacks.

Abstract: A deep learning-based Java program internal annotation generation method and system is provided. The method includes acquiring items with a Stars number ranked in the top, and extracting corresponding internal annotations and method statement lists; obtaining an <annotation, target code> pair; selecting an annotation in a Verb-dobj form; obtaining a code context associated with a target code segment; preprocessing the annotation, the target code, and the context to obtain a triplet dataset; randomly dividing the constructed dataset into a training set, a validation set, and a test set, and constructing an encoder-decoder network at the same time; enabling the training set in division to be used for model training, performing evaluation on the validation set to obtain a model with the best effect on the validation set as a target model; and predicting data in the test set with the obtained target model to generate a predicted annotation.

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

Abstract: A semiconductor structure includes a channel layer, a top source/drain feature, a bottom source/drain feature, a gate structure, and a supporting structure. The channel layer extends in a Z-direction. The top source/drain feature is over and electrically connected to the channel layer. The bottom source/drain feature is under and electrically connected to the channel layer. The gate structure laterally wraps around the channel layer. The supporting structure extends in an X-direction. The supporting structure is in contact with the channel layer, the top source/drain feature, and the bottom source/drain feature in a Y-direction.

Abstract: Embodiments of the present disclosure provides a chip and a method of forming the same and a package structure, the chip includes a base substrate and conductive bumps located on the base substrate, a planar shape of each bump has a long axis and a short axis extending through a center of the bump, a length of the long axis is greater than that of the short axis, the conductive bumps include bump unit rows each of which includes initial bump units arranged along a first direction and a first expanded bump unit located between adjacent initial bump units; the bump unit rows are arranged in a second direction, with a second expanded bump unit disposed between adjacent bump unit rows, the conductive bumps include a first pattern, a second pattern and an additional pattern formed by corresponding bumps, and each having bumps with different rotation angles.