Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.

Abstract: A method for fabricating semiconductor device includes the step of forming a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer and the free layer includes a magnesium oxide (MgO) compound. According to an embodiment of the present invention, the free layer includes a first cap layer on the barrier layer, a spacer on the first cap layer, and a second cap layer on the spacer.

Abstract: The present disclosure provides a multi-factor quantitative analysis method for deformation of a neighborhood tunnel. The method includes the following steps: analyzing monitoring data generated at a tunnel site; simulating collapse occurring at a shallow buried section of a tunnel; determining the degree of influence of each factor on the tunnel and a stratum; and determining quantitative influence of each factor on tunnel deformation. The present disclosure can not only provide an accurate theoretical basis for the construction of the shallow buried section of the small-distance tunnel, but also guarantee safety and cost saving during tunnel construction.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: Presented herein is a stage area for “focused” video that is configured to allow for dynamic layout changes during an online video conference or meeting. By providing a user interface environment that allows a user (meeting participant) to customize the stage, each participant can choose their own view, and the meeting host can fully customize a view for every participant in the meeting.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A rocker polishing apparatus for full-aperture deterministic polishing of a planar part includes a control system, a substrate, a lifting plate, a polishing module and a measuring module. The polishing module and the measuring module are arranged on the substrate. The lifting plate is arranged between the polishing module and the measuring module. The polishing module includes a rocker mechanism, a polishing pad surface dressing mechanism, a polishing pad surface profile measuring apparatus and a continuous polishing pad mechanism. The apparatus allows the material removal rate distribution of the planar part and the surface profile of the planar part be in the normalized mirror symmetry relationship by controlling the material removal rate distribution on the surface of the planar part, thereby implementing the deterministic polishing of the planar part and ensuring the efficient convergence of the surface profile of the planar part in the polishing process.

Abstract: A high-speed train derailment arresting system is provided, which includes multiple passive protection arresting devices arranged on both sides of a high-speed railway line. The passive protection arresting device includes a rigid support assembly fixed on a respective side of the high-speed railway line and a rotating protective barrel arranged on the support assembly. A structural design method for the high-speed train derailment arresting system is further provided.

Abstract: A method for data radio bearer management, the method including: transmitting a data radio bearer (DRB) setup request message to a wireless communication node; receiving a DRB setup response message from the wireless communication node, determining at least one DRB and at least one Quality of Service (QoS) flow mapped to the at least one DRB supported by the wireless communication node; and configuring the wireless communication node to support the at least one DRB and the at least one QoS flow.

Abstract: A sterilization and deodorization waste container having dual-wave band ultraviolet lamp tube includes an isolation chamber provided on an inner side of a container lid and a dual-wave band ultraviolet lamp tube installed in the isolation chamber. The dual-wave band ultraviolet lamp tube is capable of simultaneously generating a direct ultraviolet light wave and an ozone ultraviolet light wave. The isolation chamber includes a reflector housing having a light transmitting window facing an inner cavity of a container body. The dual-wave band ultraviolet lamp tube is controlled by a control circuit to turn on to generate the ultraviolets into an inner cavity of the container body while the container lid is closed and to turn off to stop generating the ultraviolet while the container lid is opened.

Abstract: A high anti-interference microsystem based on System In Package (SIP) for a power grid is provided. The high anti-interference microsystem comprises a ceramic cavity, a ceramic substrate, a magnetic cover plate, a digital signal processing circuit, an analog signal conditioning circuit and a shield, wherein the ceramic cavity supports the ceramic substrate, the magnetic cover plate is in sealed contact with the ceramic cavity, and the ceramic substrate is arranged in a cavity formed by the ceramic cavity and the magnetic cover plate; a sealed shell of the microsystem based on SIP is composed of the magnetic cover plate and the ceramic cavity; the digital signal processing circuit and the analog signal conditioning circuit are arranged on the ceramic substrate and respectively process received signals to be processed; the shield covers an outer side of the sealed shell and is used for shielding external magnetic field interference.

Abstract: A DC brushless motor is provided, which includes a housing, a motor assembly, a control board and a dividing plate. Wherein, the motor assembly is arranged in the housing, and a connecting terminal is arranged on it. The control board is arranged in the housing and electrically connected with the connecting terminal. The dividing plate is arranged in the housing and is used to divide the motor assembly from the control board. The disclosure is used to solve a problem of complicated internal wiring of a motor caused by a division of the motor and a controller of the conventional DC brushless motor.

Abstract: A COMBO ONU optical module circuit is provided, including a MCU control circuit, a XGSPON ONU circuit, and a GPON ONU circuit. The MCU control circuit includes three control units. The first control unit is configured to determine a transmission channel according to a signal level. The second control unit is configured to switch between a TX_SD_10G signal and a TX_SD_1G signal. The third control unit is configured to supply power to the GPONG ONU circuit using PWR_1G control or the XGSPONG ONU circuit using PWR_10G control. The first control unit is further configured to control the XGSPON ONU circuit and the GPON ONU circuit in an I2C communication mode. Under control of the first control unit, the XGSPON ONU circuit is configured to receive and emit a 10G optical signal, and the GPON ONU circuit is configured to receive and emit a2.5G optical signal.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Abstract: The present disclosure discloses an optical imaging lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The first lens has negative refractive power; the second lens has negative refractive power; the third lens has positive refractive power; the fourth lens has positive refractive power; the fifth lens has refractive power, and an object-side surface thereof is a concave surface; the sixth lens has refractive power; and the seventh lens has negative refractive power. An effective focal length f1 of the first lens and a total effective focal length f of the optical imaging lens assembly satisfy ?3.5<f1/f<0.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Abstract: Disclosed are a new AXL-targeting monoclonal antibody and antibody-drug conjugate. Also disclosed is a method for preparing said antibody and antibody-drug conjugate. The AXL antibody of the present invention can bind with purified human AXL protein and multiple AXL on tumor cell surface with high effectiveness and high specificity. Said humanized antibody also has high affinity and low immunogenicity. Said AXL antibody-drug conjugate has markable performance against tumors having high AXL expression.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.