Abstract: A semiconductor package includes a processor die, a storage module and a package substrate. The storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. The package substrate is on which the processor die and the storage module are disposed.

Abstract: Metric time series (MTS) data objects stored within in-memory storage are marked as inactive in response to determining that no MTS data has been received for the MTS objects within a first predetermined time period. In response to determining that an MTS object has been inactive for longer than a second predetermined time period, the MTS data object is migrated from in-memory storage to on-disk storage. Queries directed to MTS objects are first run against MTS object data stored within in-memory storage, and then against MTS object data stored within on-disk storage. In this way, an amount of in-memory storage needed to store MTS objects may be minimized, while optimizing search performance.

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

Abstract: A client identification method, an apparatus, a storage medium and a network device. The method includes: acquiring, when any client is associated with a network device, a MAC address of the client; searching and matching the MAC address from a user information table, which includes MAC addresses of all clients that have ever been associated with the network device and characteristic information corresponding to each of the MAC addresses; marking the client as successfully identified when the matching of the MAC address is successful; and marking the client as to be detected when the matching of the MAC address is failed, acquiring the characteristic information of the client from a data packet sent by the client, searching and matching the characteristic information of the client from the user information table, and identifying the client according to the matching result.

Abstract: A networking method for a household appliance, a household appliance, and a terminal device are provided. The household appliance is provided with a network module. According to the method, the network module receives router information and the account and the password of a router transmitted by a mobile terminal. The router information contains time-related data required for logging into the router; according to the router information and the account and the password of the router, log into the router.

Abstract: A variable-part liquid cooling pumping unit, including a water block set, flow guiding plate, and water block cover of a water block unit, and a chamber body of a pump housing assembly of a pump unit is provided. The chamber body includes an impeller cavity inlet, flow adjusting disc, impeller cavity, and impeller cavity outlet opening. Inlet and outlet ports are positioned on a same side. More than one water block unit and pump unit are provided and interchangeable. During operation, working fluid is sucked via the inlet port through the impeller cavity inlet, pass the flow adjusting disc, into the impeller cavity, to a plurality of curved blades of an impeller of a rotor assembly unit. From there, the working fluid travels through the impeller cavity outlet opening, flow guiding plate, and water block set, before exiting through the flow guiding plate, and outlet port.

Abstract: The present disclosure describes methods, systems and devices for establishing secure communication between a user equipment and a service application in a wireless communication. One method includes receiving, by the user equipment, an authentication and key management for service applications identifier (AKMAID) from an authentication server function (AUSF) upon successful completion of an authentication process for registering the user equipment with the communication network.

Abstract: A data receiving circuit includes: a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal; a decision feedback control module configured to generate a second sampling clock signal in response to the enable signal; a decision feedback equalization module configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and stop performing the decision feedback equalization when the enable signal is in a second level value interval; and a second amplification module configured to process the first voltage signal and the second voltage signal and output the first output signal and the second output signal.

Abstract: The present disclosure discloses a feedback method for semi-static transmission, a terminal device, a network device, a chip, a computer-readable storage medium, a computer program product and a computer program. The method includes: determining a first HARQ-ACK codebook, where the first HARQ-ACK codebook includes a second HARQ-ACK codebook and/or a third HARQ-ACK codebook that are combined, and a downlink transmission occasion window corresponding to the second HARQ-ACK codebook is independent from a downlink transmission occasion window corresponding to the third HARQ-ACK codebook; and sending the first HARQ-ACK codebook.

Abstract: A surgical stapling device includes a staple reload and a handle assembly that supports a drive rack, a motor assembly, a gear assembly, a reload select mechanism, and a safety toggle mechanism. The gear assembly is adapted to facilitate uncoupling of the motor assembly from the drive rack to allow manual movement of the drive rack. The reload select mechanism allows the length of a stroke of the drive rack to be selectively adjusted to allow the stapling device to accommodate different length staple reloads. The safety toggle mechanism is provided to move the stapling device from a non-firing state to a firing state to allow for firing of the stapling device.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: An embodiment of the disclosure provides an electronic device including multiple units. Each unit in the units includes multiple primary bonding regions and at least one reserved bonding region. Each reserved bonding region is connected to the primary bonding regions. The number of the at least one reserved bonding region is less than the number of primary bonding regions.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that generate a height map for a digital object portrayed in a digital image and further utilizes the height map to generate a shadow for the digital object. Indeed, in one or more embodiments, the disclosed systems generate (e.g., utilizing a neural network) a height map that indicates the pixels heights for pixels of a digital object portrayed in a digital image. The disclosed systems utilize the pixel heights, along with lighting information for the digital image, to determine how the pixels of the digital image project to create a shadow for the digital object. Further, in some implementations, the disclosed systems utilize the determined shadow projections to generate (e.g., utilizing another neural network) a soft shadow for the digital object. Accordingly, in some cases, the disclosed systems modify the digital image to include the shadow.

Abstract: The present invention provides an absorption-desorption based Carnot battery designed to achieve a high-efficiency, large-density, and low-loss conversion battery system for power-heat-power purpose. Based on the rational operating strategies, the current Carnot battery system design demonstrates outstanding energy storage density and round-trip efficiency, while the self-discharging loss is minimal even after prolonged standby time. The battery system of the present invention also enables further designs with flexibility in adopting different operating modes for versatile functions to provide electricity, heating, and cooling.

Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.